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Design and Simulation of a High-Order Memristor Emulator Based on Cascaded OTA Integrators.

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Title: Design and Simulation of a High-Order Memristor Emulator Based on Cascaded OTA Integrators.
Authors: Sagbas, Mehmet1 (AUTHOR) mehmet.sagbas@bakircay.edu.tr, Minaei, Shahram2 (AUTHOR) sminaei@dogus.edu.tr, Çayir, Muzaffer1 (AUTHOR) muzaffer.cayir@bakircay.edu.tr
Source: Circuits, Systems & Signal Processing. Apr2026, Vol. 45 Issue 4, p2454-2474. 21p.
Subjects: Memristors, CMOS integrated circuits, Hysteresis loop, Electronic amplifiers, Monte Carlo method, Electronic equipment
Abstract: This paper proposes a novel nth-order memristor emulator circuit that employs operational transconductance amplifiers (OTAs), grounded capacitors and a single NMOS transistor. Unlike traditional emulators, which are limited to first-order behavior, the presented design realizes higher-order memristive characteristics electronically by cascading integrator stages. This approach offers a practical way to investigate the complex memory effects that are crucial for advanced computational models and difficult to achieve with physical devices or first-order emulators. The emulator is fully resistorless and offers electronic tunability via OTA bias currents, providing memductance control. The circuit was implemented using 0.18 μm CMOS technology and validated through PSPICE simulations. The results demonstrate characteristic pinched hysteresis loops (PHLs) that vary with frequency, confirming the circuit's memristive nature. The emulator supports both incremental and decremental configurations, exhibiting robust performance under Monte Carlo and temperature variation analyses. [ABSTRACT FROM AUTHOR]
Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 193277040
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PubTypeId: academicJournal
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Design and Simulation of a High-Order Memristor Emulator Based on Cascaded OTA Integrators.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Sagbas%2C+Mehmet%22">Sagbas, Mehmet</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> mehmet.sagbas@bakircay.edu.tr</i><br /><searchLink fieldCode="AR" term="%22Minaei%2C+Shahram%22">Minaei, Shahram</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> sminaei@dogus.edu.tr</i><br /><searchLink fieldCode="AR" term="%22Çayir%2C+Muzaffer%22">Çayir, Muzaffer</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> muzaffer.cayir@bakircay.edu.tr</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. Apr2026, Vol. 45 Issue 4, p2454-2474. 21p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Memristors%22">Memristors</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Hysteresis+loop%22">Hysteresis loop</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+amplifiers%22">Electronic amplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Monte+Carlo+method%22">Monte Carlo method</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+equipment%22">Electronic equipment</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper proposes a novel nth-order memristor emulator circuit that employs operational transconductance amplifiers (OTAs), grounded capacitors and a single NMOS transistor. Unlike traditional emulators, which are limited to first-order behavior, the presented design realizes higher-order memristive characteristics electronically by cascading integrator stages. This approach offers a practical way to investigate the complex memory effects that are crucial for advanced computational models and difficult to achieve with physical devices or first-order emulators. The emulator is fully resistorless and offers electronic tunability via OTA bias currents, providing memductance control. The circuit was implemented using 0.18 μm CMOS technology and validated through PSPICE simulations. The results demonstrate characteristic pinched hysteresis loops (PHLs) that vary with frequency, confirming the circuit's memristive nature. The emulator supports both incremental and decremental configurations, exhibiting robust performance under Monte Carlo and temperature variation analyses. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s00034-025-03351-y
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 21
        StartPage: 2454
    Subjects:
      – SubjectFull: Memristors
        Type: general
      – SubjectFull: CMOS integrated circuits
        Type: general
      – SubjectFull: Hysteresis loop
        Type: general
      – SubjectFull: Electronic amplifiers
        Type: general
      – SubjectFull: Monte Carlo method
        Type: general
      – SubjectFull: Electronic equipment
        Type: general
    Titles:
      – TitleFull: Design and Simulation of a High-Order Memristor Emulator Based on Cascaded OTA Integrators.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Sagbas, Mehmet
      – PersonEntity:
          Name:
            NameFull: Minaei, Shahram
      – PersonEntity:
          Name:
            NameFull: Çayir, Muzaffer
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 04
              Text: Apr2026
              Type: published
              Y: 2026
          Identifiers:
            – Type: issn-print
              Value: 0278081X
          Numbering:
            – Type: volume
              Value: 45
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: Circuits, Systems & Signal Processing
              Type: main
ResultId 1