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深度驱动图划分的关键路径延时优化研究.

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Title: 深度驱动图划分的关键路径延时优化研究.
Alternate Title: Depth-driven graph partitioning for critical path delay optimization.
Authors: 余学雯1,2 xwyu18@163.com, 陈海燕1,2 hychen608@163.com, 黄鹏程1,2 huang.pc20@nudt.edu.cn
Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Apr2026, Vol. 48 Issue 4, p590-598. 9p.
Subjects: Microprocessor design & construction, Directed acyclic graphs, Electronic design automation, Logic circuits, Mathematical optimization
Abstract (English): In microprocessor design, critical path delay is a crucial factor that restricts the increase in the microprocessor's clock frequency and performance enhancement. The ever-increasing design complexity poses challenges to traditional optimization methods. To address this difficult issue, an automated critical path delay optimization strategy based on depth-driven graph partitioning is proposed, along with the implementation of the corresponding algorithm. The delay optimization problem is modeled as a directed acyclic graph (DAG) partitioning and selection problem. Leveraging the logic netlist designed in the semi-custom design flow, the strategy utilizes depth-driven graph partitioning to identify and select a set of sub-circuit structures with optimization potential. These sub-circuits then undergo logical reconstruction, and the corresponding logic cells in the logic netlist are replaced accordingly. Experimental results demonstrate that the proposed algorithm can optimize circuits designed by electronic design automation (EDA) tools, effectively reducing the logical depth along critical paths. Consequently, it provides an effective strategy for optimizing critical path delay within limited costs, thus aiming to achieve an improvement in microprocessor performance. [ABSTRACT FROM AUTHOR]
Abstract (Chinese): 在微处理器设计中,关键路径延时是制约微处理器主频和性能提升的重要因素,而日益增长 的设计复杂度使传统优化方法面临着挑战。针对这一难题,提出了一种自动化的深度驱动图划分的关键 路径延时优化策略,并实现了相应算法。将延时优化问题建模为有向无环图划分选择问题,基于半定制设 计流程所得的逻辑网表,利用深度驱动图划分识别并选取一批具有优化潜力的子电路结构,进行逻辑重 构,并替换逻辑网表中相应的逻辑单元集。实验结果表明,提出的算法可对电子设计自动化工具设计完成 的电路进行优化,有效降低了关键路径上的逻辑深度,进而为在有限成本下优化关键路径延时提供了一种 有效的策略,以实现微处理器性能的提升。. [ABSTRACT FROM AUTHOR]
Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: 深度驱动图划分的关键路径延时优化研究.
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  Data: In microprocessor design, critical path delay is a crucial factor that restricts the increase in the microprocessor's clock frequency and performance enhancement. The ever-increasing design complexity poses challenges to traditional optimization methods. To address this difficult issue, an automated critical path delay optimization strategy based on depth-driven graph partitioning is proposed, along with the implementation of the corresponding algorithm. The delay optimization problem is modeled as a directed acyclic graph (DAG) partitioning and selection problem. Leveraging the logic netlist designed in the semi-custom design flow, the strategy utilizes depth-driven graph partitioning to identify and select a set of sub-circuit structures with optimization potential. These sub-circuits then undergo logical reconstruction, and the corresponding logic cells in the logic netlist are replaced accordingly. Experimental results demonstrate that the proposed algorithm can optimize circuits designed by electronic design automation (EDA) tools, effectively reducing the logical depth along critical paths. Consequently, it provides an effective strategy for optimizing critical path delay within limited costs, thus aiming to achieve an improvement in microprocessor performance. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label: Abstract (Chinese)
  Group: Ab
  Data: 在微处理器设计中,关键路径延时是制约微处理器主频和性能提升的重要因素,而日益增长 的设计复杂度使传统优化方法面临着挑战。针对这一难题,提出了一种自动化的深度驱动图划分的关键 路径延时优化策略,并实现了相应算法。将延时优化问题建模为有向无环图划分选择问题,基于半定制设 计流程所得的逻辑网表,利用深度驱动图划分识别并选取一批具有优化潜力的子电路结构,进行逻辑重 构,并替换逻辑网表中相应的逻辑单元集。实验结果表明,提出的算法可对电子设计自动化工具设计完成 的电路进行优化,有效降低了关键路径上的逻辑深度,进而为在有限成本下优化关键路径延时提供了一种 有效的策略,以实现微处理器性能的提升。. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.3969/j.issn.1007-130X.2026.04.003
    Languages:
      – Code: chi
        Text: Chinese
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      Pagination:
        PageCount: 9
        StartPage: 590
    Subjects:
      – SubjectFull: Microprocessor design & construction
        Type: general
      – SubjectFull: Directed acyclic graphs
        Type: general
      – SubjectFull: Electronic design automation
        Type: general
      – SubjectFull: Logic circuits
        Type: general
      – SubjectFull: Mathematical optimization
        Type: general
    Titles:
      – TitleFull: 深度驱动图划分的关键路径延时优化研究.
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            NameFull: 余学雯
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            NameFull: 陈海燕
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            NameFull: 黄鹏程
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            – D: 01
              M: 04
              Text: Apr2026
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              Y: 2026
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