Wafer-Scale Electrical Characterization of Al/Al x O y /Al Tunnel Junctions for Process Monitoring at Room Temperature.
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| Title: | Wafer-Scale Electrical Characterization of Al/Al x O y /Al Tunnel Junctions for Process Monitoring at Room Temperature. |
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| Authors: | Lang, Simon Johann Klaus1 (AUTHOR) ignaz.eisele@emft.fraunhofer.de, Eisele, Ignaz1,2 (AUTHOR), Weber, Johannes1,3 (AUTHOR), Schewski, Alexandra1 (AUTHOR), Music, Emir1,2 (AUTHOR), Maiwald, Alwin1,3 (AUTHOR), Hahn, Martin1 (AUTHOR), Zahn, Daniela1 (AUTHOR), Luo, Zhen3 (AUTHOR), Nebrich, Lars1 (AUTHOR), Schoof, Benedikt3 (AUTHOR), Mayer, Thomas1 (AUTHOR), Sturm-Rogon, Leonhard1 (AUTHOR), Lerch, Wilfried1 (AUTHOR), Pereira, Rui Nuno1 (AUTHOR), Kutter, Christoph1,2 (AUTHOR) christoph.kutter@emft.fraunhofer.de |
| Source: | Nanomaterials (2079-4991). May2026, Vol. 16 Issue 10, p569. 11p. |
| Subjects: | Tunnel junctions (Materials science), Electric measurements, Surface defects, Josephson junctions, Complementary metal oxide semiconductors, Oxide coating |
| Abstract: | Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm2 are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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