Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates.
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| Title: | Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates. |
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| Authors: | Edward, A. Shirly1 edwards@srmist.edu.in, Sharon, R. Linie2 lr4253@srmist.edu.in, Nagarajan, P.3 nagarajp@srmist.edu.in, Dey, Rajesh4 rajesh.dey@gnsu.ac.in, Oruganti, Sai Kiran5 saisharma@lincoln.edu.my |
| Source: | Engineering Letters. Jun2026, Vol. 34 Issue 6, p2437-2446. 10p. |
| Subjects: | Computer simulation, Signal integrity (Electronics) |
| Abstract: | This paper presents a comprehensive performance analysis of single, double, and triple material gate (SMGJL, DMGJL, TMGJL) Junctionless SOI FinFETs for Analog and RF applications using Technology Computer-Aided Design (TCAD) simulations at a 30 nm gate length. This study investigates key performance metrics, including Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), ON current (Ion), OFF current (Ioff), Ion/Ioff ratio, transconductance (gm), output conductance (gd), cut-off frequency (fT), and maximum oscillation frequency (fmax) for three different gate structures. The junctionless structure, along with SOI technology, enables simplified fabrication, improved electrostatic control, and reduced leakage currents. The simulation results indicate that the TMGJL FinFET exhibits superior performance, achieving the lowest SS (59.99mV/dec), highest Ion/Ioff ratio (6.11×10), and enhanced RF figures of merit (fT = 121.98GHz, fmax = 471.16GHz), making it highly suitable for next-generation low-power and high-frequency integrated circuits. Furthermore, the inverter circuit designed using the TMGJL FinFET exhibits high noise margin (NMH) of 0.500 V and low noise margin (NML) of 0.287 V, from the voltage transfer characteristics, indicating robust noise immunity of the simulated TMGJL FinFET. The comparative analysis demonstrates the advantages of multi-material gate engineering, with the TMGJL structure providing the best trade-off among switching behaviour, current drive capability, and RF/Analog performance. [ABSTRACT FROM AUTHOR] |
| Copyright of Engineering Letters is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 194195724 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Edward%2C+A%2E+Shirly%22">Edward, A. Shirly</searchLink><relatesTo>1</relatesTo><i> edwards@srmist.edu.in</i><br /><searchLink fieldCode="AR" term="%22Sharon%2C+R%2E+Linie%22">Sharon, R. Linie</searchLink><relatesTo>2</relatesTo><i> lr4253@srmist.edu.in</i><br /><searchLink fieldCode="AR" term="%22Nagarajan%2C+P%2E%22">Nagarajan, P.</searchLink><relatesTo>3</relatesTo><i> nagarajp@srmist.edu.in</i><br /><searchLink fieldCode="AR" term="%22Dey%2C+Rajesh%22">Dey, Rajesh</searchLink><relatesTo>4</relatesTo><i> rajesh.dey@gnsu.ac.in</i><br /><searchLink fieldCode="AR" term="%22Oruganti%2C+Sai+Kiran%22">Oruganti, Sai Kiran</searchLink><relatesTo>5</relatesTo><i> saisharma@lincoln.edu.my</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Engineering+Letters%22">Engineering Letters</searchLink>. Jun2026, Vol. 34 Issue 6, p2437-2446. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+integrity+%28Electronics%29%22">Signal integrity (Electronics)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper presents a comprehensive performance analysis of single, double, and triple material gate (SMGJL, DMGJL, TMGJL) Junctionless SOI FinFETs for Analog and RF applications using Technology Computer-Aided Design (TCAD) simulations at a 30 nm gate length. This study investigates key performance metrics, including Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), ON current (Ion), OFF current (Ioff), Ion/Ioff ratio, transconductance (gm), output conductance (gd), cut-off frequency (fT), and maximum oscillation frequency (fmax) for three different gate structures. The junctionless structure, along with SOI technology, enables simplified fabrication, improved electrostatic control, and reduced leakage currents. The simulation results indicate that the TMGJL FinFET exhibits superior performance, achieving the lowest SS (59.99mV/dec), highest Ion/Ioff ratio (6.11×10), and enhanced RF figures of merit (fT = 121.98GHz, fmax = 471.16GHz), making it highly suitable for next-generation low-power and high-frequency integrated circuits. Furthermore, the inverter circuit designed using the TMGJL FinFET exhibits high noise margin (NMH) of 0.500 V and low noise margin (NML) of 0.287 V, from the voltage transfer characteristics, indicating robust noise immunity of the simulated TMGJL FinFET. The comparative analysis demonstrates the advantages of multi-material gate engineering, with the TMGJL structure providing the best trade-off among switching behaviour, current drive capability, and RF/Analog performance. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Engineering Letters is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 2437 Subjects: – SubjectFull: Computer simulation Type: general – SubjectFull: Signal integrity (Electronics) Type: general Titles: – TitleFull: Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Edward, A. Shirly – PersonEntity: Name: NameFull: Sharon, R. Linie – PersonEntity: Name: NameFull: Nagarajan, P. – PersonEntity: Name: NameFull: Dey, Rajesh – PersonEntity: Name: NameFull: Oruganti, Sai Kiran IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 1816093X Numbering: – Type: volume Value: 34 – Type: issue Value: 6 Titles: – TitleFull: Engineering Letters Type: main |
| ResultId | 1 |
