Low-Power Design and Estimation of VLSI CMOS Architectures Using approximate Arithmetic for Digital Filter Applications.
Saved in:
| Title: | Low-Power Design and Estimation of VLSI CMOS Architectures Using approximate Arithmetic for Digital Filter Applications. |
|---|---|
| Authors: | Prasath, C. Arun1 (AUTHOR) arunprasath_2004@yahoo.co.in, Shankar, C. Gowri2 (AUTHOR) cgowrishankar99@outlook.com |
| Source: | Circuits, Systems & Signal Processing. Jul2026, Vol. 45 Issue 7, p5483-5505. 23p. |
| Subjects: | CMOS integrated circuits, Power aware computing, Digital electric filters, Power measurement (Electricity), Digital filters (Mathematics), Arithmetic, Signal processing |
| Abstract: | Power estimation and minimization are inherent problems in VLSI CMOS circuit design, especially for signal processing applications such as Variable Digital Filters (VDFs), which demand high performance and low energy consumption. This work proposes an energy-efficient VLSI design for variable digital filtering by utilizing all-pass transformation (APT) techniques in combination with specially designed low-power approximate computing units: a floating-point adder (LP-AFPA) and a compressor-based multiplier (LP-CAM). These modules are made in such a way that they consume dynamic power by minimizing switching activity and logic depth. Power estimation, performed by Xilinx ISE 14.5 with an operating frequency of 210.87 MHz, shows remarkable improvements: the new architecture consumes up to 38.9% less power. It has 11.9% less delay compared to traditional approaches. The VLSI filter proposed herein was also extremely computationally accurate with 92% accuracy, 0.08 MAE, and 27.17 dB PSNR while still holding computational complexity of O(n). These observations corroborate the usability of approximation methods in reducing the power consumption of VLSI CMOS technology indicating that the approach proposed is exceedingly appropriate for implementing next-generation low-power digital filters. [ABSTRACT FROM AUTHOR] |
| Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 194867700 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Low-Power Design and Estimation of VLSI CMOS Architectures Using approximate Arithmetic for Digital Filter Applications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Prasath%2C+C%2E+Arun%22">Prasath, C. Arun</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> arunprasath_2004@yahoo.co.in</i><br /><searchLink fieldCode="AR" term="%22Shankar%2C+C%2E+Gowri%22">Shankar, C. Gowri</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> cgowrishankar99@outlook.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. Jul2026, Vol. 45 Issue 7, p5483-5505. 23p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Power+aware+computing%22">Power aware computing</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electric+filters%22">Digital electric filters</searchLink><br /><searchLink fieldCode="DE" term="%22Power+measurement+%28Electricity%29%22">Power measurement (Electricity)</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+filters+%28Mathematics%29%22">Digital filters (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Arithmetic%22">Arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Power estimation and minimization are inherent problems in VLSI CMOS circuit design, especially for signal processing applications such as Variable Digital Filters (VDFs), which demand high performance and low energy consumption. This work proposes an energy-efficient VLSI design for variable digital filtering by utilizing all-pass transformation (APT) techniques in combination with specially designed low-power approximate computing units: a floating-point adder (LP-AFPA) and a compressor-based multiplier (LP-CAM). These modules are made in such a way that they consume dynamic power by minimizing switching activity and logic depth. Power estimation, performed by Xilinx ISE 14.5 with an operating frequency of 210.87 MHz, shows remarkable improvements: the new architecture consumes up to 38.9% less power. It has 11.9% less delay compared to traditional approaches. The VLSI filter proposed herein was also extremely computationally accurate with 92% accuracy, 0.08 MAE, and 27.17 dB PSNR while still holding computational complexity of O(n). These observations corroborate the usability of approximation methods in reducing the power consumption of VLSI CMOS technology indicating that the approach proposed is exceedingly appropriate for implementing next-generation low-power digital filters. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=194867700 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00034-025-03371-8 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 23 StartPage: 5483 Subjects: – SubjectFull: CMOS integrated circuits Type: general – SubjectFull: Power aware computing Type: general – SubjectFull: Digital electric filters Type: general – SubjectFull: Power measurement (Electricity) Type: general – SubjectFull: Digital filters (Mathematics) Type: general – SubjectFull: Arithmetic Type: general – SubjectFull: Signal processing Type: general Titles: – TitleFull: Low-Power Design and Estimation of VLSI CMOS Architectures Using approximate Arithmetic for Digital Filter Applications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Prasath, C. Arun – PersonEntity: Name: NameFull: Shankar, C. Gowri IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 0278081X Numbering: – Type: volume Value: 45 – Type: issue Value: 7 Titles: – TitleFull: Circuits, Systems & Signal Processing Type: main |
| ResultId | 1 |
