Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems.

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Bibliographic Details
Title:	Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems.
Authors:	YANG, Xuanyuan^1,2 1392786661@qq.com, JIANG, Jianwu³ 47955024@qq.com, WANG, Yihuai² yihuaiw@suda.edu.cn
Source:	Technical Gazette / Tehnički Vjesnik. 2026, Vol. 33 Issue 3, p949-955. 7p.
Subjects:	Computer memory management, Flash memory, Dynamic random access memory, Embedded computer systems
Abstract:	This paper presents a systematic implementation and analysis of a multi-stage BIOS boot process for the D1-H RISC-V application processor, addressing the critical challenges of limited on-chip storage and complex memory management requirements in modern embedded systems. We propose a three-stage boot architecture integrating on-chip BROM firmware, Secondary Program Loader (SPL), and main program execution, alongside an efficient storage allocation strategy utilizing external Nand Flash and DRAM. Our implementation demonstrates significant technical innovations in three key areas: (1) a modular storage structure design that optimizes memory utilization across different boot stages, achieving efficient code migration between Nand Flash (128 MB) and DRAM (512 MB); (2) an adaptive boot process that enables flexible configuration for various startup scenarios, supporting both development and production environments; and (3) a novel engineering framework that enhances code portability and maintainability. Performance analysis reveals that our implementation achieves a boot time of 10 ms for the complete startup sequence, with memory utilization efficiency of 15% compared to conventional approaches. The system successfully manages code migration between storage media with a transfer rate of 100 MB/s, demonstrating reliable operation across multiple test scenarios. We validate our design through comprehensive testing on the ADL-D1-H platform, showing successful integration with development tools and supporting direct program downloads through serial ports. This work provides practical insights for BIOS design in RISC-V systems and establishes a replicable framework for implementing efficient boot processes in resource-constrained embedded environments. The proposed solution eliminates the need for external download devices and enables direct serial port programming, significantly simplifying development, research, and remote update processes. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper presents a systematic implementation and analysis of a multi-stage BIOS boot process for the D1-H RISC-V application processor, addressing the critical challenges of limited on-chip storage and complex memory management requirements in modern embedded systems. We propose a three-stage boot architecture integrating on-chip BROM firmware, Secondary Program Loader (SPL), and main program execution, alongside an efficient storage allocation strategy utilizing external Nand Flash and DRAM. Our implementation demonstrates significant technical innovations in three key areas: (1) a modular storage structure design that optimizes memory utilization across different boot stages, achieving efficient code migration between Nand Flash (128 MB) and DRAM (512 MB); (2) an adaptive boot process that enables flexible configuration for various startup scenarios, supporting both development and production environments; and (3) a novel engineering framework that enhances code portability and maintainability. Performance analysis reveals that our implementation achieves a boot time of 10 ms for the complete startup sequence, with memory utilization efficiency of 15% compared to conventional approaches. The system successfully manages code migration between storage media with a transfer rate of 100 MB/s, demonstrating reliable operation across multiple test scenarios. We validate our design through comprehensive testing on the ADL-D1-H platform, showing successful integration with development tools and supporting direct program downloads through serial ports. This work provides practical insights for BIOS design in RISC-V systems and establishes a replicable framework for implementing efficient boot processes in resource-constrained embedded environments. The proposed solution eliminates the need for external download devices and enables direct serial port programming, significantly simplifying development, research, and remote update processes. [ABSTRACT FROM AUTHOR]
ISSN:	13303651
DOI:	10.17559/TV-20241010002048