Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems.
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| Title: | Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems. |
|---|---|
| Authors: | YANG, Xuanyuan1,2 1392786661@qq.com, JIANG, Jianwu3 47955024@qq.com, WANG, Yihuai2 yihuaiw@suda.edu.cn |
| Source: | Technical Gazette / Tehnički Vjesnik. 2026, Vol. 33 Issue 3, p949-955. 7p. |
| Subjects: | Computer memory management, Flash memory, Dynamic random access memory, Embedded computer systems |
| Abstract: | This paper presents a systematic implementation and analysis of a multi-stage BIOS boot process for the D1-H RISC-V application processor, addressing the critical challenges of limited on-chip storage and complex memory management requirements in modern embedded systems. We propose a three-stage boot architecture integrating on-chip BROM firmware, Secondary Program Loader (SPL), and main program execution, alongside an efficient storage allocation strategy utilizing external Nand Flash and DRAM. Our implementation demonstrates significant technical innovations in three key areas: (1) a modular storage structure design that optimizes memory utilization across different boot stages, achieving efficient code migration between Nand Flash (128 MB) and DRAM (512 MB); (2) an adaptive boot process that enables flexible configuration for various startup scenarios, supporting both development and production environments; and (3) a novel engineering framework that enhances code portability and maintainability. Performance analysis reveals that our implementation achieves a boot time of 10 ms for the complete startup sequence, with memory utilization efficiency of 15% compared to conventional approaches. The system successfully manages code migration between storage media with a transfer rate of 100 MB/s, demonstrating reliable operation across multiple test scenarios. We validate our design through comprehensive testing on the ADL-D1-H platform, showing successful integration with development tools and supporting direct program downloads through serial ports. This work provides practical insights for BIOS design in RISC-V systems and establishes a replicable framework for implementing efficient boot processes in resource-constrained embedded environments. The proposed solution eliminates the need for external download devices and enables direct serial port programming, significantly simplifying development, research, and remote update processes. [ABSTRACT FROM AUTHOR] |
| Copyright of Technical Gazette / Tehnički Vjesnik is the property of Tehnicki Vjesnik and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 195131780 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22YANG%2C+Xuanyuan%22">YANG, Xuanyuan</searchLink><relatesTo>1,2</relatesTo><i> 1392786661@qq.com</i><br /><searchLink fieldCode="AR" term="%22JIANG%2C+Jianwu%22">JIANG, Jianwu</searchLink><relatesTo>3</relatesTo><i> 47955024@qq.com</i><br /><searchLink fieldCode="AR" term="%22WANG%2C+Yihuai%22">WANG, Yihuai</searchLink><relatesTo>2</relatesTo><i> yihuaiw@suda.edu.cn</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Technical+Gazette+%2F+Tehnički+Vjesnik%22">Technical Gazette / Tehnički Vjesnik</searchLink>. 2026, Vol. 33 Issue 3, p949-955. 7p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+memory+management%22">Computer memory management</searchLink><br /><searchLink fieldCode="DE" term="%22Flash+memory%22">Flash memory</searchLink><br /><searchLink fieldCode="DE" term="%22Dynamic+random+access+memory%22">Dynamic random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper presents a systematic implementation and analysis of a multi-stage BIOS boot process for the D1-H RISC-V application processor, addressing the critical challenges of limited on-chip storage and complex memory management requirements in modern embedded systems. We propose a three-stage boot architecture integrating on-chip BROM firmware, Secondary Program Loader (SPL), and main program execution, alongside an efficient storage allocation strategy utilizing external Nand Flash and DRAM. Our implementation demonstrates significant technical innovations in three key areas: (1) a modular storage structure design that optimizes memory utilization across different boot stages, achieving efficient code migration between Nand Flash (128 MB) and DRAM (512 MB); (2) an adaptive boot process that enables flexible configuration for various startup scenarios, supporting both development and production environments; and (3) a novel engineering framework that enhances code portability and maintainability. Performance analysis reveals that our implementation achieves a boot time of 10 ms for the complete startup sequence, with memory utilization efficiency of 15% compared to conventional approaches. The system successfully manages code migration between storage media with a transfer rate of 100 MB/s, demonstrating reliable operation across multiple test scenarios. We validate our design through comprehensive testing on the ADL-D1-H platform, showing successful integration with development tools and supporting direct program downloads through serial ports. This work provides practical insights for BIOS design in RISC-V systems and establishes a replicable framework for implementing efficient boot processes in resource-constrained embedded environments. The proposed solution eliminates the need for external download devices and enables direct serial port programming, significantly simplifying development, research, and remote update processes. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Technical Gazette / Tehnički Vjesnik is the property of Tehnicki Vjesnik and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.17559/TV-20241010002048 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 7 StartPage: 949 Subjects: – SubjectFull: Computer memory management Type: general – SubjectFull: Flash memory Type: general – SubjectFull: Dynamic random access memory Type: general – SubjectFull: Embedded computer systems Type: general Titles: – TitleFull: Implementation and Performance Analysis of a Multi-Stage BIOS Boot Process for D1-H RISC-V Systems. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: YANG, Xuanyuan – PersonEntity: Name: NameFull: JIANG, Jianwu – PersonEntity: Name: NameFull: WANG, Yihuai IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: 2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 13303651 Numbering: – Type: volume Value: 33 – Type: issue Value: 3 Titles: – TitleFull: Technical Gazette / Tehnički Vjesnik Type: main |
| ResultId | 1 |
