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The effect of die attach voiding on the thermal resistance of chip level packages

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Title: The effect of die attach voiding on the thermal resistance of chip level packages
Authors: Fleischer, Amy S.1 amy.fleischer@villanova.edu, Chang, Li-hsin2, Johnson, Barry C.1 barry.johnson@villanova.edu
Source: Microelectronics Reliability. May2006, Vol. 46 Issue 5/6, p794-804. 11p.
Subjects: Electronic packaging, Dies (Metalworking), Temperature coefficient of electric resistance, Electronic equipment
Abstract: Abstract: The presence of voids in the die bond region is known to adversely affect the thermal resistance of the packaged chip-level device. Unfortunately, such voids are easily formed in the solder layer during manufacturing, and are found to nucleate, grow and coalesce with thermal cycling. Although the relationship between package thermal resistance and voids has been examined extensively, little data exist concerning the precise effects of void size, configuration and position. The present study allows the experimental investigation of these effects through application of an innovative experimental technique that carefully controls void geometry and distribution. The results show that for small, random voids, the thermal resistance, θ jc , increases linearly with void volume percentage, V %, according to the equation θ jc =0.007V +1.4987, and for large, contiguous voids the increase follows the exponential relationship, θ jc =1.427e0.015V . At 73% voiding, θ jc was found to increase 30% and 200% for random and contiguous voids, respectively. [Copyright &y& Elsevier]
Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 20263108
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: The effect of die attach voiding on the thermal resistance of chip level packages
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  Data: <searchLink fieldCode="AR" term="%22Fleischer%2C+Amy+S%2E%22">Fleischer, Amy S.</searchLink><relatesTo>1</relatesTo><i> amy.fleischer@villanova.edu</i><br /><searchLink fieldCode="AR" term="%22Chang%2C+Li-hsin%22">Chang, Li-hsin</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Johnson%2C+Barry+C%2E%22">Johnson, Barry C.</searchLink><relatesTo>1</relatesTo><i> barry.johnson@villanova.edu</i>
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  Data: <searchLink fieldCode="JN" term="%22Microelectronics+Reliability%22">Microelectronics Reliability</searchLink>. May2006, Vol. 46 Issue 5/6, p794-804. 11p.
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  Data: <searchLink fieldCode="DE" term="%22Electronic+packaging%22">Electronic packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Dies+%28Metalworking%29%22">Dies (Metalworking)</searchLink><br /><searchLink fieldCode="DE" term="%22Temperature+coefficient+of+electric+resistance%22">Temperature coefficient of electric resistance</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+equipment%22">Electronic equipment</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Abstract: The presence of voids in the die bond region is known to adversely affect the thermal resistance of the packaged chip-level device. Unfortunately, such voids are easily formed in the solder layer during manufacturing, and are found to nucleate, grow and coalesce with thermal cycling. Although the relationship between package thermal resistance and voids has been examined extensively, little data exist concerning the precise effects of void size, configuration and position. The present study allows the experimental investigation of these effects through application of an innovative experimental technique that carefully controls void geometry and distribution. The results show that for small, random voids, the thermal resistance, θ jc , increases linearly with void volume percentage, V %, according to the equation θ jc =0.007V +1.4987, and for large, contiguous voids the increase follows the exponential relationship, θ jc =1.427e0.015V . At 73% voiding, θ jc was found to increase 30% and 200% for random and contiguous voids, respectively. [Copyright &y& Elsevier]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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        Type: general
      – SubjectFull: Dies (Metalworking)
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      – SubjectFull: Temperature coefficient of electric resistance
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      – SubjectFull: Electronic equipment
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              Text: May2006
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