Verification and fault synthesis algorithm at switch-level
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| Title: | Verification and fault synthesis algorithm at switch-level |
|---|---|
| Authors: | Javaheri, M. Reza1, Sedaghat, Reza rsedagha@ee.ryerson.ca, Kant, Leo1, Zalev, Jason1 |
| Source: | Microprocessors & Microsystems. Jun2006, Vol. 30 Issue 4, p199-208. 10p. |
| Subjects: | Algorithms, Complementary metal oxide semiconductors, Technology, Algebra |
| Abstract: | Abstract: Switch-level simulation has become a common means for accurate modelling of CMOS circuit behaviour and testing. This paper presents an algorithm for modelling CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Another advantage of this algorithm is its application in the mapping of single and multiple faults from switch-level to gate level as well as its function as a multi level model. Multiple faults can be of the same or different types. Experimental results show that the algorithm is successful and reliable for CMOS technology. [Copyright &y& Elsevier] |
| Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 21050582 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Verification and fault synthesis algorithm at switch-level – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Javaheri%2C+M%2E+Reza%22">Javaheri, M. Reza</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Sedaghat%2C+Reza%22">Sedaghat, Reza</searchLink><i> rsedagha@ee.ryerson.ca</i><br /><searchLink fieldCode="AR" term="%22Kant%2C+Leo%22">Kant, Leo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zalev%2C+Jason%22">Zalev, Jason</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Jun2006, Vol. 30 Issue 4, p199-208. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Technology%22">Technology</searchLink><br /><searchLink fieldCode="DE" term="%22Algebra%22">Algebra</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract: Switch-level simulation has become a common means for accurate modelling of CMOS circuit behaviour and testing. This paper presents an algorithm for modelling CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Another advantage of this algorithm is its application in the mapping of single and multiple faults from switch-level to gate level as well as its function as a multi level model. Multiple faults can be of the same or different types. Experimental results show that the algorithm is successful and reliable for CMOS technology. [Copyright &y& Elsevier] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=21050582 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.micpro.2005.12.002 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 199 Subjects: – SubjectFull: Algorithms Type: general – SubjectFull: Complementary metal oxide semiconductors Type: general – SubjectFull: Technology Type: general – SubjectFull: Algebra Type: general Titles: – TitleFull: Verification and fault synthesis algorithm at switch-level Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Javaheri, M. Reza – PersonEntity: Name: NameFull: Sedaghat, Reza – PersonEntity: Name: NameFull: Kant, Leo – PersonEntity: Name: NameFull: Zalev, Jason IsPartOfRelationships: – BibEntity: Dates: – D: 06 M: 06 Text: Jun2006 Type: published Y: 2006 Identifiers: – Type: issn-print Value: 01419331 Numbering: – Type: volume Value: 30 – Type: issue Value: 4 Titles: – TitleFull: Microprocessors & Microsystems Type: main |
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