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Inside the Intel 10.1 Compilers: New Threadizer and New Vectorizer for Intel Core2 Processors.

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Title: Inside the Intel 10.1 Compilers: New Threadizer and New Vectorizer for Intel Core2 Processors.
Authors: Xinmin Tian1, Su, Ernesto1, Kreitzer, David1, Saito, Hideki1, Krishnaiyer, Rakesh1, Kanhere, Abhay1, Ng, John1, Chu-Cheow Lim2, Ghosh, Somnath2
Source: Intel Technology Journal. Nov2007, Vol. 11 Issue 4, p263-274. 12p. 2 Diagrams, 1 Chart, 2 Graphs.
Subjects: Compilers (Computer programs), Intel computers, Computer software, Program transformation, Microprocessors
Abstract: The fast introduction of the Intel® Core™2 Duo and Quad processors to the mass market has drawn attention to threadization (a.k.a. parallelization) and vectorization of the existing code in many application domains. In fact, multi-core processor vendors are eager to enable their users to exploit various levels of parallelism in order to harness the additional compute resources of multi-core processors. The Intel® C++/Fortran compiler provides an essential tool for unleashing the power of Intel Core 2 Duo and Quad processors. This is accomplished by means of high-level loop optimizations and scalar optimizations to exploit multi-core processors and single-instructionmultiple-data (SIMD) instructions, combined with advanced code generation, that is built on an intimate knowledge of micro-architectural performance aspects. In this paper we outline the design and implementation of a new threadizer and vectorizer inside the Intel® 10.1 compilers, and we also provide an overview of the enhanced high-level loop optimizations and the low-level code generation used to obtain higher performance on platforms based on Intel Core 2 Duo and Quad processors. Significant performance gains are shown using the SPEC CPU2006* suite running on a system configured with two Intel® quad-core processors. [ABSTRACT FROM AUTHOR]
Copyright of Intel Technology Journal is the property of Intel Corporation and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: <searchLink fieldCode="JN" term="%22Intel+Technology+Journal%22">Intel Technology Journal</searchLink>. Nov2007, Vol. 11 Issue 4, p263-274. 12p. 2 Diagrams, 1 Chart, 2 Graphs.
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  Data: The fast introduction of the Intel® Core™2 Duo and Quad processors to the mass market has drawn attention to threadization (a.k.a. parallelization) and vectorization of the existing code in many application domains. In fact, multi-core processor vendors are eager to enable their users to exploit various levels of parallelism in order to harness the additional compute resources of multi-core processors. The Intel® C++/Fortran compiler provides an essential tool for unleashing the power of Intel Core 2 Duo and Quad processors. This is accomplished by means of high-level loop optimizations and scalar optimizations to exploit multi-core processors and single-instructionmultiple-data (SIMD) instructions, combined with advanced code generation, that is built on an intimate knowledge of micro-architectural performance aspects. In this paper we outline the design and implementation of a new threadizer and vectorizer inside the Intel® 10.1 compilers, and we also provide an overview of the enhanced high-level loop optimizations and the low-level code generation used to obtain higher performance on platforms based on Intel Core 2 Duo and Quad processors. Significant performance gains are shown using the SPEC CPU2006* suite running on a system configured with two Intel® quad-core processors. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Intel Technology Journal is the property of Intel Corporation and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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