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Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.

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Title: Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.
Authors: Fürtler, Johannes1, Rössler, Peter2, Brodersen, Jörg1, Nachtnebel, Herbert3, Mayer, Konrad J.1, Cadek, Gerhard4, Eckel, Christian4
Source: EURASIP Journal on Embedded Systems. 2007 Special Issue 2, p1-10. 10p. 8 Diagrams, 2 Charts.
Subjects: Embedded computer systems, Optical quality control, Field programmable gate arrays, Signal processing, Algorithms
Abstract: This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results. [ABSTRACT FROM AUTHOR]
Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.
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  Data: <searchLink fieldCode="JN" term="%22EURASIP+Journal+on+Embedded+Systems%22">EURASIP Journal on Embedded Systems</searchLink>. 2007 Special Issue 2, p1-10. 10p. 8 Diagrams, 2 Charts.
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  Data: <searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink><br /><searchLink fieldCode="DE" term="%22Optical+quality+control%22">Optical quality control</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink>
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  Data: This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1155/2007/71794
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        Text: English
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      – SubjectFull: Field programmable gate arrays
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              Text: 2007 Special Issue 2
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