View in EDS PDF Full Text

Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.

Saved in:
Bibliographic Details
Title: Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.
Authors: Verma, Akshat1 akshatverma@in.ibm.com, Sen, Sandeep2 ssen@cse.iitd.ernet.in
Source: Journal of Supercomputing. Aug2008, Vol. 45 Issue 2, p205-235. 31p. 2 Diagrams, 1 Chart, 2 Graphs.
Subjects: Memory hierarchy (Computer science), Data transmission systems, Broadband communication systems, Computer storage devices, Algorithms, Computer programming, Bandwidths
Abstract: Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, []). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Links:
  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 32679563
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Verma%2C+Akshat%22">Verma, Akshat</searchLink><relatesTo>1</relatesTo><i> akshatverma@in.ibm.com</i><br /><searchLink fieldCode="AR" term="%22Sen%2C+Sandeep%22">Sen, Sandeep</searchLink><relatesTo>2</relatesTo><i> ssen@cse.iitd.ernet.in</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Aug2008, Vol. 45 Issue 2, p205-235. 31p. 2 Diagrams, 1 Chart, 2 Graphs.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Memory+hierarchy+%28Computer+science%29%22">Memory hierarchy (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Data+transmission+systems%22">Data transmission systems</searchLink><br /><searchLink fieldCode="DE" term="%22Broadband+communication+systems%22">Broadband communication systems</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink><br /><searchLink fieldCode="DE" term="%22Bandwidths%22">Bandwidths</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, []). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=32679563
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s11227-007-0170-0
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 31
        StartPage: 205
    Subjects:
      – SubjectFull: Memory hierarchy (Computer science)
        Type: general
      – SubjectFull: Data transmission systems
        Type: general
      – SubjectFull: Broadband communication systems
        Type: general
      – SubjectFull: Computer storage devices
        Type: general
      – SubjectFull: Algorithms
        Type: general
      – SubjectFull: Computer programming
        Type: general
      – SubjectFull: Bandwidths
        Type: general
    Titles:
      – TitleFull: Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Verma, Akshat
      – PersonEntity:
          Name:
            NameFull: Sen, Sandeep
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 08
              Text: Aug2008
              Type: published
              Y: 2008
          Identifiers:
            – Type: issn-print
              Value: 09208542
          Numbering:
            – Type: volume
              Value: 45
            – Type: issue
              Value: 2
          Titles:
            – TitleFull: Journal of Supercomputing
              Type: main
ResultId 1