Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models.
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| Title: | Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models. |
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| Authors: | Ping Yang1,2 yangping1964@163.com, Wei Li1 |
| Source: | International Journal of Numerical Modelling. Jan/Feb2009, Vol. 22 Issue 1, p43-55. 13p. 7 Diagrams, 2 Charts, 8 Graphs. |
| Subjects: | Chip scale packaging, Electronic packaging, Thermal stresses, Finite element method, Computer simulation |
| Abstract: | The objective of this paper is to investigate stress and strain of a special scale package-substrate on chip for reliability evaluation or manufacture strategy in deep-seated situation. A two-dimensional model with one-half of cross-section (2D model) and a three-dimensional model with one-fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP-SOC under the condition of the standard industry thermal cycling temperature -40 to125°C. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright © 2008 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Numerical Modelling is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 35678196 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ping+Yang%22">Ping Yang</searchLink><relatesTo>1,2</relatesTo><i> yangping1964@163.com</i><br /><searchLink fieldCode="AR" term="%22Wei+Li%22">Wei Li</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Numerical+Modelling%22">International Journal of Numerical Modelling</searchLink>. Jan/Feb2009, Vol. 22 Issue 1, p43-55. 13p. 7 Diagrams, 2 Charts, 8 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+packaging%22">Electronic packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Thermal+stresses%22">Thermal stresses</searchLink><br /><searchLink fieldCode="DE" term="%22Finite+element+method%22">Finite element method</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The objective of this paper is to investigate stress and strain of a special scale package-substrate on chip for reliability evaluation or manufacture strategy in deep-seated situation. A two-dimensional model with one-half of cross-section (2D model) and a three-dimensional model with one-fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP-SOC under the condition of the standard industry thermal cycling temperature -40 to125°C. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright © 2008 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of International Journal of Numerical Modelling is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/jnm.694 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 43 Subjects: – SubjectFull: Chip scale packaging Type: general – SubjectFull: Electronic packaging Type: general – SubjectFull: Thermal stresses Type: general – SubjectFull: Finite element method Type: general – SubjectFull: Computer simulation Type: general Titles: – TitleFull: Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ping Yang – PersonEntity: Name: NameFull: Wei Li IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan/Feb2009 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 08943370 Numbering: – Type: volume Value: 22 – Type: issue Value: 1 Titles: – TitleFull: International Journal of Numerical Modelling Type: main |
| ResultId | 1 |
