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Reducing clock jitter by using Muller-C elements.

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Title: Reducing clock jitter by using Muller-C elements.
Authors: Winstead, C.1 winstead@engineering.usu.edu, Hamoui, M. El1
Source: Electronics Letters (Institution of Engineering & Technology). 1/29/2009, Vol. 45 Issue 3, p150-151. 2p. 1 Diagram, 2 Graphs.
Subjects: Electronics, Very large scale circuit integration, Digital-to-analog converters, Digital electronics, Digital incremental plotters
Abstract: A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element's output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogue-to-digital conversion, and in clock distribution networks for VLSI systems. [ABSTRACT FROM AUTHOR]
Copyright of Electronics Letters (Institution of Engineering & Technology) is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 36332327
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element's output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogue-to-digital conversion, and in clock distribution networks for VLSI systems. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Electronics Letters (Institution of Engineering & Technology) is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1049/el:20093196
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      – SubjectFull: Very large scale circuit integration
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      – SubjectFull: Digital-to-analog converters
        Type: general
      – SubjectFull: Digital electronics
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      – SubjectFull: Digital incremental plotters
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      – TitleFull: Reducing clock jitter by using Muller-C elements.
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              Text: 1/29/2009
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