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Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing.

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Title: Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing.
Authors: Boldt, Marian1, Traulsen, Claus1 ctr@informatik.uni-kiel.de, von Hanxleden, Reinhard1
Source: EURASIP Journal on Embedded Systems. 1/7/2009, p1-21. 21p. 10 Diagrams, 3 Charts, 1 Graph.
Subjects: Application-specific instruction-set processors, Synchronous data transmission systems, Compilers (Computer programs), Digital communications, Language & education, Interlanguage (Language learning)
Abstract: The recently proposed reactive processing architectures are characterized by instruction set architectures (ISAs) that directly support reactive control fow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their worst-case reaction time (WCRT). We present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading. Building on this compilation approach, we also present a procedure for statically determining tight, safe upper bounds on the WCRT. Experimental results indicate the practicality of this approach, withWCRT estimates to be accurate within 22% on average. [ABSTRACT FROM AUTHOR]
Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: <searchLink fieldCode="JN" term="%22EURASIP+Journal+on+Embedded+Systems%22">EURASIP Journal on Embedded Systems</searchLink>. 1/7/2009, p1-21. 21p. 10 Diagrams, 3 Charts, 1 Graph.
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  Data: The recently proposed reactive processing architectures are characterized by instruction set architectures (ISAs) that directly support reactive control fow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their worst-case reaction time (WCRT). We present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading. Building on this compilation approach, we also present a procedure for statically determining tight, safe upper bounds on the WCRT. Experimental results indicate the practicality of this approach, withWCRT estimates to be accurate within 22% on average. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              M: 01
              Text: 1/7/2009
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