APA (7th ed.) Citation

Baronti, F., Lazzeri, A., Roncella, R., & Saletti, R. (2009). FPGA/DSP-based implementation of a high-performance multi-channel counter. Journal of Systems Architecture, 55(5/6), 310. https://doi.org/10.1016/j.sysarc.2009.03.002

Chicago Style (17th ed.) Citation

Baronti, F., A. Lazzeri, R. Roncella, and R. Saletti. "FPGA/DSP-based Implementation of a High-performance Multi-channel Counter." Journal of Systems Architecture 55, no. 5/6 (2009): 310. https://doi.org/10.1016/j.sysarc.2009.03.002.

MLA (9th ed.) Citation

Baronti, F., et al. "FPGA/DSP-based Implementation of a High-performance Multi-channel Counter." Journal of Systems Architecture, vol. 55, no. 5/6, 2009, p. 310, https://doi.org/10.1016/j.sysarc.2009.03.002.