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FPGA/DSP-based implementation of a high-performance multi-channel counter

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Title: FPGA/DSP-based implementation of a high-performance multi-channel counter
Authors: Baronti, F.1, Lazzeri, A.1, Roncella, R.1, Saletti, R. r.saletti@iet.unipi.it
Source: Journal of Systems Architecture. May2009, Vol. 55 Issue 5/6, p310-316. 7p.
Subjects: Photon detectors, Counters (Computer science), Robust control, Experimental design
Abstract: Abstract: A high-performance configurable multi-channel counter is presented. The system has been implemented on a small-size and low-cost Commercial-Off-The-Shelf (COTS) FPGA/DSP-based board, and features 64 input channels, a maximum counting rate of 45MHz, and a minimum integration window (time resolution) of 24 μs with a 23b counting depth. In particular, the time resolution depends on both the selected counting bit-depth and the number of acquisition channels: indeed, with a 8b counting depth, the time resolution reaches the value of 8 μs if all the 64 input channels are enabled, whereas it lowers to 378ns if only 2 channels are used. Thanks to its flexible architecture and performance, the system is suitable in highly demanding photon counting applications based on SPAD arrays, as well as in many other scientific experiments. Moreover, the collected counting results are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a even higher degree of flexibility. Finally, a theoretical model of general use which immediately provides the overall system performance is described. The model is then validated by the reported experimental results. [Copyright &y& Elsevier]
Copyright of Journal of Systems Architecture is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 40637109
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PubType: Academic Journal
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  Data: FPGA/DSP-based implementation of a high-performance multi-channel counter
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  Data: <searchLink fieldCode="AR" term="%22Baronti%2C+F%2E%22">Baronti, F.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Lazzeri%2C+A%2E%22">Lazzeri, A.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Roncella%2C+R%2E%22">Roncella, R.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Saletti%2C+R%2E%22">Saletti, R.</searchLink><i> r.saletti@iet.unipi.it</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Systems+Architecture%22">Journal of Systems Architecture</searchLink>. May2009, Vol. 55 Issue 5/6, p310-316. 7p.
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  Data: <searchLink fieldCode="DE" term="%22Photon+detectors%22">Photon detectors</searchLink><br /><searchLink fieldCode="DE" term="%22Counters+%28Computer+science%29%22">Counters (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Robust+control%22">Robust control</searchLink><br /><searchLink fieldCode="DE" term="%22Experimental+design%22">Experimental design</searchLink>
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  Data: Abstract: A high-performance configurable multi-channel counter is presented. The system has been implemented on a small-size and low-cost Commercial-Off-The-Shelf (COTS) FPGA/DSP-based board, and features 64 input channels, a maximum counting rate of 45MHz, and a minimum integration window (time resolution) of 24 μs with a 23b counting depth. In particular, the time resolution depends on both the selected counting bit-depth and the number of acquisition channels: indeed, with a 8b counting depth, the time resolution reaches the value of 8 μs if all the 64 input channels are enabled, whereas it lowers to 378ns if only 2 channels are used. Thanks to its flexible architecture and performance, the system is suitable in highly demanding photon counting applications based on SPAD arrays, as well as in many other scientific experiments. Moreover, the collected counting results are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a even higher degree of flexibility. Finally, a theoretical model of general use which immediately provides the overall system performance is described. The model is then validated by the reported experimental results. [Copyright &y& Elsevier]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of Journal of Systems Architecture is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.sysarc.2009.03.002
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      – Code: eng
        Text: English
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        Type: general
      – SubjectFull: Counters (Computer science)
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      – SubjectFull: Robust control
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      – SubjectFull: Experimental design
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              Text: May2009
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              Y: 2009
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