Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism.
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| Title: | Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. |
|---|---|
| Authors: | Balkan, Aydin O.1 balkanay@umd.edu, Gang Qu1 gangqu@umd.edu, Vishkin, Uzi1 vishkin@umd.edu |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2009, Vol. 17 Issue 10, p1419-1432. 14p. 3 Black and White Photographs, 6 Charts, 2 Graphs. |
| Subjects: | Parallel processing, Netcentric computing, Integrated circuit interconnections, Multiprocessors, Topology |
| Abstract: | In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 90-nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 44477604 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Balkan%2C+Aydin+O%2E%22">Balkan, Aydin O.</searchLink><relatesTo>1</relatesTo><i> balkanay@umd.edu</i><br /><searchLink fieldCode="AR" term="%22Gang+Qu%22">Gang Qu</searchLink><relatesTo>1</relatesTo><i> gangqu@umd.edu</i><br /><searchLink fieldCode="AR" term="%22Vishkin%2C+Uzi%22">Vishkin, Uzi</searchLink><relatesTo>1</relatesTo><i> vishkin@umd.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Oct2009, Vol. 17 Issue 10, p1419-1432. 14p. 3 Black and White Photographs, 6 Charts, 2 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Netcentric+computing%22">Netcentric computing</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+interconnections%22">Integrated circuit interconnections</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprocessors%22">Multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Topology%22">Topology</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 90-nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2008.2003999 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 1419 Subjects: – SubjectFull: Parallel processing Type: general – SubjectFull: Netcentric computing Type: general – SubjectFull: Integrated circuit interconnections Type: general – SubjectFull: Multiprocessors Type: general – SubjectFull: Topology Type: general Titles: – TitleFull: Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Balkan, Aydin O. – PersonEntity: Name: NameFull: Gang Qu – PersonEntity: Name: NameFull: Vishkin, Uzi IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2009 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 17 – Type: issue Value: 10 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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