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A total standard WIP estimation method for wafer fabrication.

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Bibliographic Details
Title: A total standard WIP estimation method for wafer fabrication.
Authors: Yu-Hsin Lin, Ching-En Lee
Source: European Journal of Operational Research. 05/16/2001, Vol. 131 Issue 1, p78-94. 17p. 1 Diagram, 13 Charts, 1 Graph.
Subjects: Semiconductor industry, Algorithms, Queuing theory, Network analysis (Planning), Production control
Geographic Terms: Taiwan
Abstract: Proposes a queuing network-based algorithm for estimating the total standard work-in-process (WIP) level so that a fixed-WIP release algorithm control policy can apply. Simulation model of a real-world wafer fabrication factory in Taiwan; Assumptions under the queuing network model.
Database: Engineering Source
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  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 4737447
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
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  Data: A total standard WIP estimation method for wafer fabrication.
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  Data: <searchLink fieldCode="AR" term="%22Yu-Hsin+Lin%22">Yu-Hsin Lin</searchLink><br /><searchLink fieldCode="AR" term="%22Ching-En+Lee%22">Ching-En Lee</searchLink>
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  Data: <searchLink fieldCode="JN" term="%22European+Journal+of+Operational+Research%22">European Journal of Operational Research</searchLink>. 05/16/2001, Vol. 131 Issue 1, p78-94. 17p. 1 Diagram, 13 Charts, 1 Graph.
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  Data: <searchLink fieldCode="DE" term="%22Semiconductor+industry%22">Semiconductor industry</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Queuing+theory%22">Queuing theory</searchLink><br /><searchLink fieldCode="DE" term="%22Network+analysis+%28Planning%29%22">Network analysis (Planning)</searchLink><br /><searchLink fieldCode="DE" term="%22Production+control%22">Production control</searchLink>
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  Data: <searchLink fieldCode="DE" term="%22Taiwan%22">Taiwan</searchLink>
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  Data: Proposes a queuing network-based algorithm for estimating the total standard work-in-process (WIP) level so that a fixed-WIP release algorithm control policy can apply. Simulation model of a real-world wafer fabrication factory in Taiwan; Assumptions under the queuing network model.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=4737447
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1016/S0377-2217(99)00446-4
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 17
        StartPage: 78
    Subjects:
      – SubjectFull: Semiconductor industry
        Type: general
      – SubjectFull: Algorithms
        Type: general
      – SubjectFull: Queuing theory
        Type: general
      – SubjectFull: Network analysis (Planning)
        Type: general
      – SubjectFull: Production control
        Type: general
      – SubjectFull: Taiwan
        Type: general
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      – TitleFull: A total standard WIP estimation method for wafer fabrication.
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          Name:
            NameFull: Yu-Hsin Lin
      – PersonEntity:
          Name:
            NameFull: Ching-En Lee
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            – D: 16
              M: 05
              Text: 05/16/2001
              Type: published
              Y: 2001
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              Value: 131
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            – TitleFull: European Journal of Operational Research
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