Logic synthesis based on decomposition for CPLDs
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| Title: | Logic synthesis based on decomposition for CPLDs |
|---|---|
| Authors: | Kania, Dariusz Dariusz.Kania@polsl.pl, Milik, Adam1 Adam.Milik@polsl.pl |
| Source: | Microprocessors & Microsystems. Feb2010, Vol. 34 Issue 1, p25-38. 14p. |
| Subjects: | Programmable logic devices, Decomposition method, PAL (Computer program language), Mathematical programming, Graph coloring, Computer logic, Logic circuits, Scientific experimentation |
| Abstract: | Abstract: The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction. [Copyright &y& Elsevier] |
| Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 47461991 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Logic synthesis based on decomposition for CPLDs – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kania%2C+Dariusz%22">Kania, Dariusz</searchLink><i> Dariusz.Kania@polsl.pl</i><br /><searchLink fieldCode="AR" term="%22Milik%2C+Adam%22">Milik, Adam</searchLink><relatesTo>1</relatesTo><i> Adam.Milik@polsl.pl</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Feb2010, Vol. 34 Issue 1, p25-38. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Programmable+logic+devices%22">Programmable logic devices</searchLink><br /><searchLink fieldCode="DE" term="%22Decomposition+method%22">Decomposition method</searchLink><br /><searchLink fieldCode="DE" term="%22PAL+%28Computer+program+language%29%22">PAL (Computer program language)</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+programming%22">Mathematical programming</searchLink><br /><searchLink fieldCode="DE" term="%22Graph+coloring%22">Graph coloring</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+logic%22">Computer logic</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Scientific+experimentation%22">Scientific experimentation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract: The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction. [Copyright &y& Elsevier] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.micpro.2009.11.002 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 25 Subjects: – SubjectFull: Programmable logic devices Type: general – SubjectFull: Decomposition method Type: general – SubjectFull: PAL (Computer program language) Type: general – SubjectFull: Mathematical programming Type: general – SubjectFull: Graph coloring Type: general – SubjectFull: Computer logic Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Scientific experimentation Type: general Titles: – TitleFull: Logic synthesis based on decomposition for CPLDs Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kania, Dariusz – PersonEntity: Name: NameFull: Milik, Adam IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2010 Type: published Y: 2010 Identifiers: – Type: issn-print Value: 01419331 Numbering: – Type: volume Value: 34 – Type: issue Value: 1 Titles: – TitleFull: Microprocessors & Microsystems Type: main |
| ResultId | 1 |
