Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders.

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Title: Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders.
Authors: Passas, Georgios1 Georgios.Passas@pace.com, Freear, Steven1, Fawcett, Darren2
Source: International Journal of Electronics. Jan2010, Vol. 97 Issue 1, p31-43. 13p. 6 Diagrams, 5 Graphs.
Subjects: Field programmable gate arrays, Wireless communications, Electronic circuit design, Integrated circuits, Electric power consumption
Abstract: Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), 'A Simple Transmit Diversity Technique for Wireless Communications', IEEE Journal on Selected Areas in Communications, 16:55-108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Electronics is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders.
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  Data: <searchLink fieldCode="AR" term="%22Passas%2C+Georgios%22">Passas, Georgios</searchLink><relatesTo>1</relatesTo><i> Georgios.Passas@pace.com</i><br /><searchLink fieldCode="AR" term="%22Freear%2C+Steven%22">Freear, Steven</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Fawcett%2C+Darren%22">Fawcett, Darren</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics%22">International Journal of Electronics</searchLink>. Jan2010, Vol. 97 Issue 1, p31-43. 13p. 6 Diagrams, 5 Graphs.
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  Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Wireless+communications%22">Wireless communications</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuit+design%22">Electronic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+power+consumption%22">Electric power consumption</searchLink>
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  Label: Abstract
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  Data: Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), 'A Simple Transmit Diversity Technique for Wireless Communications', IEEE Journal on Selected Areas in Communications, 16:55-108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of International Journal of Electronics is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1080/00207210902894787
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      – Code: eng
        Text: English
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        PageCount: 13
        StartPage: 31
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      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Wireless communications
        Type: general
      – SubjectFull: Electronic circuit design
        Type: general
      – SubjectFull: Integrated circuits
        Type: general
      – SubjectFull: Electric power consumption
        Type: general
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      – TitleFull: Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders.
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              Text: Jan2010
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