Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.

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Bibliographic Details
Title:	Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
Authors:	Yongsoon Lee¹, Younhee Choi¹, Seok-Bum Ko¹ seokbum.ko@usask.ca, Moon Ho Lee²
Source:	EURASIP Journal on Embedded Systems. 1/1/2009, Special section p1-11. 11p. 5 Diagrams, 11 Charts, 5 Graphs.
Subjects:	Computer arithmetic & logic units, Artificial neural networks, Floating-point arithmetic, Cost control, Errors
Abstract:	This paper implements a field programmable gate array- (FPGA-) based face detector using a neural network (NN) and the bitwidth reduced floating-point arithmetic unit (FPU). The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), is developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN are designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, are compared. The analytical results and the experimental results show conformity of shape. We demonstrate that incremented reductions in the number of bits used can produce significant cost reductions including area, speed, and power. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper implements a field programmable gate array- (FPGA-) based face detector using a neural network (NN) and the bitwidth reduced floating-point arithmetic unit (FPU). The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), is developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN are designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, are compared. The analytical results and the experimental results show conformity of shape. We demonstrate that incremented reductions in the number of bits used can produce significant cost reductions including area, speed, and power. [ABSTRACT FROM AUTHOR]
ISSN:	16873955
DOI:	10.1155/2009/258921