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Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.

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Title: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
Authors: Yongsoon Lee1, Younhee Choi1, Seok-Bum Ko1 seokbum.ko@usask.ca, Moon Ho Lee2
Source: EURASIP Journal on Embedded Systems. 1/1/2009, Special section p1-11. 11p. 5 Diagrams, 11 Charts, 5 Graphs.
Subjects: Computer arithmetic & logic units, Artificial neural networks, Floating-point arithmetic, Cost control, Errors
Abstract: This paper implements a field programmable gate array- (FPGA-) based face detector using a neural network (NN) and the bitwidth reduced floating-point arithmetic unit (FPU). The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), is developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN are designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, are compared. The analytical results and the experimental results show conformity of shape. We demonstrate that incremented reductions in the number of bits used can produce significant cost reductions including area, speed, and power. [ABSTRACT FROM AUTHOR]
Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
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  Data: <searchLink fieldCode="JN" term="%22EURASIP+Journal+on+Embedded+Systems%22">EURASIP Journal on Embedded Systems</searchLink>. 1/1/2009, Special section p1-11. 11p. 5 Diagrams, 11 Charts, 5 Graphs.
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  Data: This paper implements a field programmable gate array- (FPGA-) based face detector using a neural network (NN) and the bitwidth reduced floating-point arithmetic unit (FPU). The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), is developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN are designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, are compared. The analytical results and the experimental results show conformity of shape. We demonstrate that incremented reductions in the number of bits used can produce significant cost reductions including area, speed, and power. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of EURASIP Journal on Embedded Systems is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1155/2009/258921
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        Text: English
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      – SubjectFull: Artificial neural networks
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      – SubjectFull: Floating-point arithmetic
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      – TitleFull: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
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            – D: 01
              M: 01
              Text: 1/1/2009
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