Register allocation with instruction scheduling for VLIW-architectures.
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| Title: | Register allocation with instruction scheduling for VLIW-architectures. |
|---|---|
| Authors: | Ivanov, D.1 dimanovs@gmail.com |
| Source: | Programming & Computer Software. Nov2010, Vol. 36 Issue 6, p363-367. 5p. |
| Subjects: | Registers (Computers), Optimizing compilers, Dynamic storage allocation (Computer science), Instructional systems, Algorithms, Information networks, Matrices (Mathematics) |
| Abstract: | Interaction between the phases of register allocation and instruction scheduling are often considered in publications devoted to optimizations for the final stage of compilation. Typically, it is proposed to adapt one of the phase for needs of another without their combination into a single unit. However, their integration can essentially reduce the time of operation and enhance the performance of the resulting code. This study describes an attempt to combine these phases as completely as possible with account for the features of static scheduling for VLIW-architectures. [ABSTRACT FROM AUTHOR] |
| Copyright of Programming & Computer Software is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 55388127 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Register allocation with instruction scheduling for VLIW-architectures. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ivanov%2C+D%2E%22">Ivanov, D.</searchLink><relatesTo>1</relatesTo><i> dimanovs@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Programming+%26+Computer+Software%22">Programming & Computer Software</searchLink>. Nov2010, Vol. 36 Issue 6, p363-367. 5p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Registers+%28Computers%29%22">Registers (Computers)</searchLink><br /><searchLink fieldCode="DE" term="%22Optimizing+compilers%22">Optimizing compilers</searchLink><br /><searchLink fieldCode="DE" term="%22Dynamic+storage+allocation+%28Computer+science%29%22">Dynamic storage allocation (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Instructional+systems%22">Instructional systems</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Information+networks%22">Information networks</searchLink><br /><searchLink fieldCode="DE" term="%22Matrices+%28Mathematics%29%22">Matrices (Mathematics)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Interaction between the phases of register allocation and instruction scheduling are often considered in publications devoted to optimizations for the final stage of compilation. Typically, it is proposed to adapt one of the phase for needs of another without their combination into a single unit. However, their integration can essentially reduce the time of operation and enhance the performance of the resulting code. This study describes an attempt to combine these phases as completely as possible with account for the features of static scheduling for VLIW-architectures. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Programming & Computer Software is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1134/S0361768810060058 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 363 Subjects: – SubjectFull: Registers (Computers) Type: general – SubjectFull: Optimizing compilers Type: general – SubjectFull: Dynamic storage allocation (Computer science) Type: general – SubjectFull: Instructional systems Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Information networks Type: general – SubjectFull: Matrices (Mathematics) Type: general Titles: – TitleFull: Register allocation with instruction scheduling for VLIW-architectures. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ivanov, D. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2010 Type: published Y: 2010 Identifiers: – Type: issn-print Value: 03617688 Numbering: – Type: volume Value: 36 – Type: issue Value: 6 Titles: – TitleFull: Programming & Computer Software Type: main |
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