View in EDS PDF Full Text

Region-based parallelization of irregular reductions on explicitly managed memory hierarchies.

Saved in:
Bibliographic Details
Title: Region-based parallelization of irregular reductions on explicitly managed memory hierarchies.
Authors: Seonggun Kim1 sg.kim@kaist.ac.kr, Hwansoo Han2 hhan@skku.edu, Kwang-Moo Choe1 choe@kaist.ac.kr
Source: Journal of Supercomputing. Apr2011, Vol. 56 Issue 1, p25-55. 31p. 9 Charts, 10 Graphs.
Subjects: Memory hierarchy (Computer science), Computer memory management, Computer storage devices, Computer architecture, Embedded computer systems, Technological innovations
Abstract: Multicore architectures are evolving with the promise of extreme performance for the classes of applications that require high performance and large bandwidth of memory. Irregular reduction is one of important computation patterns for many complex scientific applications, and it typically requires high performance and large bandwidth of memory. In this article, we propose region-based parallelization techniques for irregular reductions on multicore architectures with explicitly managed memory hierarchies. Managing memory hierarchy in software requires a lot of programming efforts and tends to be error-prone. The difficulties are even worse for applications with irregular data access patterns. To relieve the burden of memory management from programmers, we develop abstractions, particularly targeted to irregular reduction, for structuring parallel tasks, mapping the parallel tasks to processing units and scheduling data transfers between the memory hierarchies. Our framework employs iteration reordering based on regions of data along with dynamic scheduling of parallel tasks. We experimentally evaluate the effectiveness of our techniques for irregular reduction kernels on the Cell processor embedded in a Sony PlayStation3. Experimental results show the speedups of 8 to 14 on the six available SPEs. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Links:
  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 59698982
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Region-based parallelization of irregular reductions on explicitly managed memory hierarchies.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Seonggun+Kim%22">Seonggun Kim</searchLink><relatesTo>1</relatesTo><i> sg.kim@kaist.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Hwansoo+Han%22">Hwansoo Han</searchLink><relatesTo>2</relatesTo><i> hhan@skku.edu</i><br /><searchLink fieldCode="AR" term="%22Kwang-Moo+Choe%22">Kwang-Moo Choe</searchLink><relatesTo>1</relatesTo><i> choe@kaist.ac.kr</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Apr2011, Vol. 56 Issue 1, p25-55. 31p. 9 Charts, 10 Graphs.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Memory+hierarchy+%28Computer+science%29%22">Memory hierarchy (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+memory+management%22">Computer memory management</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink><br /><searchLink fieldCode="DE" term="%22Technological+innovations%22">Technological innovations</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Multicore architectures are evolving with the promise of extreme performance for the classes of applications that require high performance and large bandwidth of memory. Irregular reduction is one of important computation patterns for many complex scientific applications, and it typically requires high performance and large bandwidth of memory. In this article, we propose region-based parallelization techniques for irregular reductions on multicore architectures with explicitly managed memory hierarchies. Managing memory hierarchy in software requires a lot of programming efforts and tends to be error-prone. The difficulties are even worse for applications with irregular data access patterns. To relieve the burden of memory management from programmers, we develop abstractions, particularly targeted to irregular reduction, for structuring parallel tasks, mapping the parallel tasks to processing units and scheduling data transfers between the memory hierarchies. Our framework employs iteration reordering based on regions of data along with dynamic scheduling of parallel tasks. We experimentally evaluate the effectiveness of our techniques for irregular reduction kernels on the Cell processor embedded in a Sony PlayStation3. Experimental results show the speedups of 8 to 14 on the six available SPEs. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=59698982
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s11227-009-0340-3
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 31
        StartPage: 25
    Subjects:
      – SubjectFull: Memory hierarchy (Computer science)
        Type: general
      – SubjectFull: Computer memory management
        Type: general
      – SubjectFull: Computer storage devices
        Type: general
      – SubjectFull: Computer architecture
        Type: general
      – SubjectFull: Embedded computer systems
        Type: general
      – SubjectFull: Technological innovations
        Type: general
    Titles:
      – TitleFull: Region-based parallelization of irregular reductions on explicitly managed memory hierarchies.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Seonggun Kim
      – PersonEntity:
          Name:
            NameFull: Hwansoo Han
      – PersonEntity:
          Name:
            NameFull: Kwang-Moo Choe
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 04
              Text: Apr2011
              Type: published
              Y: 2011
          Identifiers:
            – Type: issn-print
              Value: 09208542
          Numbering:
            – Type: volume
              Value: 56
            – Type: issue
              Value: 1
          Titles:
            – TitleFull: Journal of Supercomputing
              Type: main
ResultId 1