Application-Specific Networks-on-Chips Design.
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| Title: | Application-Specific Networks-on-Chips Design. |
|---|---|
| Authors: | Janidarmian, Majid1 jani@srbiau.ac.ir, Fekr, Atena Roshan2 atena.roshanfekr@mail.mcgill.ca, Bokharaei, Vahhab Samadi3 v.samadi@sbu.ac.ir |
| Source: | IAENG International Journal of Computer Science. Mar2011, Vol. 38 Issue 1, p16-25. 10p. |
| Subjects: | Networks on a chip, Embedded computer system design & construction, Algorithms, Routing (Computer network management), Computer networks, Fault tolerance (Engineering), Application software, Energy consumption |
| Abstract: | Mapping algorithm, which is an important phase of an NoC design tries to map most frequent and most critical communications in such a way that minimize the physical distance between the source and destination nodes. The objective of this paper is to achieve an application-specific NoC design that minimizes the communication cost and improves the fault tolerant properties. First, a heuristic mapping algorithm that produces a set of different mappings in a reasonable time is presented. Although this mapping does not explore the design space thoroughly, it considers a part of design space, which in general minimizes the communication costs of solutions while yielding optimum communication costs in some cases. Comparison of the communication cost results makes it obvious that final solutions found by our proposed approach outperform the results of other methods, which proposed in literature. Then, the used routing algorithm and the concept, vulnerability index, which is considered as a criterion for estimating the fault-tolerance of mapped application, are presented in details. Lower communication cost leads to an NoC with better metrics such as energy consumption and latency; and reducing the vulnerability index optimizes fault tolerant properties of NoC. In order to yield a mapping which considers trade-offs between these two parameters, a linear function is defined and introduced. It is also observed that more flexibility to prioritize solutions within the design space is possible by adjusting a set of if-then rules in fuzzy logic. [ABSTRACT FROM AUTHOR] |
| Copyright of IAENG International Journal of Computer Science is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Items | – Name: Title Label: Title Group: Ti Data: Application-Specific Networks-on-Chips Design. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Janidarmian%2C+Majid%22">Janidarmian, Majid</searchLink><relatesTo>1</relatesTo><i> jani@srbiau.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Fekr%2C+Atena+Roshan%22">Fekr, Atena Roshan</searchLink><relatesTo>2</relatesTo><i> atena.roshanfekr@mail.mcgill.ca</i><br /><searchLink fieldCode="AR" term="%22Bokharaei%2C+Vahhab+Samadi%22">Bokharaei, Vahhab Samadi</searchLink><relatesTo>3</relatesTo><i> v.samadi@sbu.ac.ir</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IAENG+International+Journal+of+Computer+Science%22">IAENG International Journal of Computer Science</searchLink>. Mar2011, Vol. 38 Issue 1, p16-25. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Networks+on+a+chip%22">Networks on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+system+design+%26+construction%22">Embedded computer system design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+%28Computer+network+management%29%22">Routing (Computer network management)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+networks%22">Computer networks</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Application+software%22">Application software</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Mapping algorithm, which is an important phase of an NoC design tries to map most frequent and most critical communications in such a way that minimize the physical distance between the source and destination nodes. The objective of this paper is to achieve an application-specific NoC design that minimizes the communication cost and improves the fault tolerant properties. First, a heuristic mapping algorithm that produces a set of different mappings in a reasonable time is presented. Although this mapping does not explore the design space thoroughly, it considers a part of design space, which in general minimizes the communication costs of solutions while yielding optimum communication costs in some cases. Comparison of the communication cost results makes it obvious that final solutions found by our proposed approach outperform the results of other methods, which proposed in literature. Then, the used routing algorithm and the concept, vulnerability index, which is considered as a criterion for estimating the fault-tolerance of mapped application, are presented in details. Lower communication cost leads to an NoC with better metrics such as energy consumption and latency; and reducing the vulnerability index optimizes fault tolerant properties of NoC. In order to yield a mapping which considers trade-offs between these two parameters, a linear function is defined and introduced. It is also observed that more flexibility to prioritize solutions within the design space is possible by adjusting a set of if-then rules in fuzzy logic. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IAENG International Journal of Computer Science is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 16 Subjects: – SubjectFull: Networks on a chip Type: general – SubjectFull: Embedded computer system design & construction Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Routing (Computer network management) Type: general – SubjectFull: Computer networks Type: general – SubjectFull: Fault tolerance (Engineering) Type: general – SubjectFull: Application software Type: general – SubjectFull: Energy consumption Type: general Titles: – TitleFull: Application-Specific Networks-on-Chips Design. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Janidarmian, Majid – PersonEntity: Name: NameFull: Fekr, Atena Roshan – PersonEntity: Name: NameFull: Bokharaei, Vahhab Samadi IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2011 Type: published Y: 2011 Identifiers: – Type: issn-print Value: 1819656X Numbering: – Type: volume Value: 38 – Type: issue Value: 1 Titles: – TitleFull: IAENG International Journal of Computer Science Type: main |
| ResultId | 1 |
