Bibliographic Details
| Title: |
A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control |
| Authors: |
Plessas, F.1,2 fotis.plessas@analogies.eu, Davrazos, E.2, Alexandropoulos, A.2, Birbas, M.2, Kikidis, J.2 |
| Source: |
Computers & Electrical Engineering. Mar2012, Vol. 38 Issue 2, p206-216. 11p. |
| Subjects: |
Computer software termination, Robust control, Electric resistors, Electric impedance, Temperature effect, Ports (Electronic computer system), Computer input-output equipment, Electric potential |
| Abstract: |
Abstract: A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations. [Copyright &y& Elsevier] |
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| Database: |
Engineering Source |
