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A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control

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Title: A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Authors: Plessas, F.1,2 fotis.plessas@analogies.eu, Davrazos, E.2, Alexandropoulos, A.2, Birbas, M.2, Kikidis, J.2
Source: Computers & Electrical Engineering. Mar2012, Vol. 38 Issue 2, p206-216. 11p.
Subjects: Computer software termination, Robust control, Electric resistors, Electric impedance, Temperature effect, Ports (Electronic computer system), Computer input-output equipment, Electric potential
Abstract: Abstract: A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations. [Copyright &y& Elsevier]
Copyright of Computers & Electrical Engineering is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 73276322
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
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  Data: <searchLink fieldCode="DE" term="%22Computer+software+termination%22">Computer software termination</searchLink><br /><searchLink fieldCode="DE" term="%22Robust+control%22">Robust control</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+resistors%22">Electric resistors</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+impedance%22">Electric impedance</searchLink><br /><searchLink fieldCode="DE" term="%22Temperature+effect%22">Temperature effect</searchLink><br /><searchLink fieldCode="DE" term="%22Ports+%28Electronic+computer+system%29%22">Ports (Electronic computer system)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+potential%22">Electric potential</searchLink>
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  Data: Abstract: A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations. [Copyright &y& Elsevier]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Computers & Electrical Engineering is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1016/j.compeleceng.2011.12.012
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      – Code: eng
        Text: English
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        Type: general
      – SubjectFull: Robust control
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      – SubjectFull: Electric resistors
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      – SubjectFull: Electric impedance
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      – SubjectFull: Temperature effect
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      – SubjectFull: Ports (Electronic computer system)
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      – SubjectFull: Computer input-output equipment
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      – SubjectFull: Electric potential
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      – TitleFull: A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
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              Text: Mar2012
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