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Modified Collision-Free Interleavers for High Speed Turbo Decoding.

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Title: Modified Collision-Free Interleavers for High Speed Turbo Decoding.
Authors: Ren, Defeng1 defengren@gmail.com, Ge, Jianhua1 jhge@xidian.edu.cn, Li, Jing1 jli@xidian.edu.cn
Source: Wireless Personal Communications. Feb2013, Vol. 68 Issue 3, p939-948. 10p.
Subjects: Decoders & decoding, Code division multiple access, Decoders (Electronics), Telecommunication systems, Decoding algorithms
Abstract: Inter-window shuffle (IWS) interleavers are a class of collision-free (CF) interleavers that have been applied to parallel turbo decoding. In this paper, we present modified IWS (M-IWS) interleavers that can further increase turbo decoding throughput only at the expense of slight performance degradation. By deriving the number of M-IWS interleavers, we demonstrate that the number is much smaller than that of IWS interleavers, whereas they both have a very simple algebraic representation. Further, it is shown by analysis that under given conditions, storage requirements of M-IWS interleavers can be reduced to only 368 storage bits for variable interleaving lengths. In order to realize parallel outputs of the on-line interleaving addresses, a low-complexity architecture design of M-IWS interleavers for parallel turbo decoding is proposed, which also supports variable interleaving lengths. Therefore, the M-IWS interleavers are very suitable for the turbo decoder in next generation communication systems with the high data rate and low latency requirements. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:Inter-window shuffle (IWS) interleavers are a class of collision-free (CF) interleavers that have been applied to parallel turbo decoding. In this paper, we present modified IWS (M-IWS) interleavers that can further increase turbo decoding throughput only at the expense of slight performance degradation. By deriving the number of M-IWS interleavers, we demonstrate that the number is much smaller than that of IWS interleavers, whereas they both have a very simple algebraic representation. Further, it is shown by analysis that under given conditions, storage requirements of M-IWS interleavers can be reduced to only 368 storage bits for variable interleaving lengths. In order to realize parallel outputs of the on-line interleaving addresses, a low-complexity architecture design of M-IWS interleavers for parallel turbo decoding is proposed, which also supports variable interleaving lengths. Therefore, the M-IWS interleavers are very suitable for the turbo decoder in next generation communication systems with the high data rate and low latency requirements. [ABSTRACT FROM AUTHOR]
ISSN:09296212
DOI:10.1007/s11277-011-0491-4