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Memory Map: A Multiprocessor Cache Simulator.

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Title: Memory Map: A Multiprocessor Cache Simulator.
Authors: Mittal, Shaily1, Nitin2 delnitin@ieee.org
Source: Journal of Electrical & Computer Engineering. 2012, p1-12. 12p. 5 Diagrams, 4 Charts, 7 Graphs.
Subjects: Memory maps (Computer science), Multiprocessors, Cache memory, Integrated circuits, Computer architecture, Embedded computer systems, Systems design, Application software
Abstract: Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cachemiss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cachemiss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Journal of Electrical & Computer Engineering is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Type: general
      – SubjectFull: Multiprocessors
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      – SubjectFull: Cache memory
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      – SubjectFull: Integrated circuits
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      – SubjectFull: Application software
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              Text: 2012
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