Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers.
Saved in:
| Title: | Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. |
|---|---|
| Authors: | Maniatakos, Michail1, Kudva, Prabhakar2, Fleischer, Bruce M.2, Makris, Yiorgos3 |
| Source: | IEEE Transactions on Computers. Jul2013, Vol. 62 Issue 7, p1376-1388. 13p. |
| Subjects: | Concurrent error detection, Floating-point arithmetic, IEEE Computer Society, Computer input-output equipment, Microprocessors, Data analysis, Transient analysis |
| Abstract: | We present a nonintrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating-point unit (FPU). The proposed method is based on the observation that control logic errors lead to extensive data path corruption and affect, with high probability, the exponent part of the IEEE-754 floating-point representation. Thus, exponent monitoring can be utilized to detect errors in the control logic of the FPU. Predicting the exponent involves relatively simple operations; therefore, our method incurs significantly lower overhead than the classical approach of duplicating the control logic of the FPU. Indeed, experimental results on the openSPARC T1 processor using SPEC2006FP benchmarks show that as compared to control logic duplication, which incurs an area overhead of 17.9 percent of the FPU size, our method incurs an area overhead of only 5.8 percent yet still achieves detection of over 93 percent of transient errors in the FPU control logic. Moreover, the proposed method offers the ancillary benefit of also detecting 98.1 percent of the data path errors that affect the exponent, which cannot be detected via duplication of control logic. Finally, when combined with a classical residue code-based method for the fraction, our method leads to a complete CED solution for the entire FPU which provides a coverage of 94.1 percent of all errors at an area cost of 16.32 percent of the FPU size. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 87803672 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Maniatakos%2C+Michail%22">Maniatakos, Michail</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kudva%2C+Prabhakar%22">Kudva, Prabhakar</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Fleischer%2C+Bruce+M%2E%22">Fleischer, Bruce M.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Makris%2C+Yiorgos%22">Makris, Yiorgos</searchLink><relatesTo>3</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>. Jul2013, Vol. 62 Issue 7, p1376-1388. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Floating-point+arithmetic%22">Floating-point arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22IEEE+Computer+Society%22">IEEE Computer Society</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Data+analysis%22">Data analysis</searchLink><br /><searchLink fieldCode="DE" term="%22Transient+analysis%22">Transient analysis</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: We present a nonintrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating-point unit (FPU). The proposed method is based on the observation that control logic errors lead to extensive data path corruption and affect, with high probability, the exponent part of the IEEE-754 floating-point representation. Thus, exponent monitoring can be utilized to detect errors in the control logic of the FPU. Predicting the exponent involves relatively simple operations; therefore, our method incurs significantly lower overhead than the classical approach of duplicating the control logic of the FPU. Indeed, experimental results on the openSPARC T1 processor using SPEC2006FP benchmarks show that as compared to control logic duplication, which incurs an area overhead of 17.9 percent of the FPU size, our method incurs an area overhead of only 5.8 percent yet still achieves detection of over 93 percent of transient errors in the FPU control logic. Moreover, the proposed method offers the ancillary benefit of also detecting 98.1 percent of the data path errors that affect the exponent, which cannot be detected via duplication of control logic. Finally, when combined with a classical residue code-based method for the fraction, our method leads to a complete CED solution for the entire FPU which provides a coverage of 94.1 percent of all errors at an area cost of 16.32 percent of the FPU size. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=87803672 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TC.2012.81 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 1376 Subjects: – SubjectFull: Concurrent error detection Type: general – SubjectFull: Floating-point arithmetic Type: general – SubjectFull: IEEE Computer Society Type: general – SubjectFull: Computer input-output equipment Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Data analysis Type: general – SubjectFull: Transient analysis Type: general Titles: – TitleFull: Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Maniatakos, Michail – PersonEntity: Name: NameFull: Kudva, Prabhakar – PersonEntity: Name: NameFull: Fleischer, Bruce M. – PersonEntity: Name: NameFull: Makris, Yiorgos IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 00189340 Numbering: – Type: volume Value: 62 – Type: issue Value: 7 Titles: – TitleFull: IEEE Transactions on Computers Type: main |
| ResultId | 1 |
