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A new compaction strategy for enhancing the utilization of reconfigurable chips.

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Title: A new compaction strategy for enhancing the utilization of reconfigurable chips.
Authors: Saleh, A.1 aisaleh@yahoo.com
Source: International Journal of Advanced Manufacturing Technology. Jul2013, Vol. 67 Issue 1-4, p455-473. 19p. 16 Diagrams, 10 Charts, 14 Graphs.
Subjects: Strategic planning, Programmable circuits, Field programmable gate arrays, Logic circuits, Mathematical formulas, Fragmentation reactions
Abstract: Field programmable gate arrays (FPGAs) are designed to implement any logic circuit with the ability to host several independent tasks simultaneously. They inherit reconfigurability from their programmable architecture. However, designs are usually dynamic and the arrival times of tasks may be unknown in advance. Accordingly, FPGA should have the ability to: (1) place incoming tasks at run time, and (2) compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations. It tries to move running tasks closer to each others to free a sufficient area for hosting more tasks. Unfortunately, traditional compaction techniques suffer from internal and external fragmentations. This paper introduces a novel puzzle-based compaction (PBC) technique. PBC is a shape-aware technique that is the first to take the task shape into consideration. Hence, it succeeds not only to eliminate the internal fragmentations but also to minimize the external fragmentations. Moreover, the paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by hosting a set of tasks inside the reconfigurable chip. Experimental results have shown that PBC outperforms recent compaction techniques in which the chip utilization has reached 87 %. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Advanced Manufacturing Technology is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: <searchLink fieldCode="DE" term="%22Strategic+planning%22">Strategic planning</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+circuits%22">Programmable circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+formulas%22">Mathematical formulas</searchLink><br /><searchLink fieldCode="DE" term="%22Fragmentation+reactions%22">Fragmentation reactions</searchLink>
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  Data: Field programmable gate arrays (FPGAs) are designed to implement any logic circuit with the ability to host several independent tasks simultaneously. They inherit reconfigurability from their programmable architecture. However, designs are usually dynamic and the arrival times of tasks may be unknown in advance. Accordingly, FPGA should have the ability to: (1) place incoming tasks at run time, and (2) compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations. It tries to move running tasks closer to each others to free a sufficient area for hosting more tasks. Unfortunately, traditional compaction techniques suffer from internal and external fragmentations. This paper introduces a novel puzzle-based compaction (PBC) technique. PBC is a shape-aware technique that is the first to take the task shape into consideration. Hence, it succeeds not only to eliminate the internal fragmentations but also to minimize the external fragmentations. Moreover, the paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by hosting a set of tasks inside the reconfigurable chip. Experimental results have shown that PBC outperforms recent compaction techniques in which the chip utilization has reached 87 %. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of International Journal of Advanced Manufacturing Technology is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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