Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
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| Title: | Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. |
|---|---|
| Authors: | Mathew, Jimson1 Jimson.Mathew@bristol.ac.uk, Mohanty, Saraju P.2 saraju.mohanty@unt.edu, Banerjee, Shibaji1 shibaji100@gmail.com, Pradhan, Dhiraj K.1 pradhan@compsci.bristol.ac.uk, Jabir, A.M.3 ajabir@brookes.ac.uk |
| Source: | Computers & Electrical Engineering. May2013, Vol. 39 Issue 4, p1077-1087. 11p. |
| Subjects: | Concurrent error detection, Cryptography, Cyberterrorism, Switching circuits, Fault tolerance (Engineering), Algorithms, Signal processing |
| Abstract: | Abstract: Thwarting severe cryptographic hardware attacks requires new approaches to logic and physical designs. This paper presents a systematic design approach to fault tolerant cryptographic hardware designs by combining the concurrent error detection and correction, and uniform switching activity cells. The effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance of stream cipher algorithms with error detection and correction was studied by synthesising the designs on FPGA and custom Integrated Circuits. The hardware building blocks are investigated to minimise switching activity of a circuit for all possible inputs and their transitions by adding redundant gates and increasing the overall number of signal transitions. The overheads of the proposed approach are also discussed. [Copyright &y& Elsevier] |
| Copyright of Computers & Electrical Engineering is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 89117364 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Mathew%2C+Jimson%22">Mathew, Jimson</searchLink><relatesTo>1</relatesTo><i> Jimson.Mathew@bristol.ac.uk</i><br /><searchLink fieldCode="AR" term="%22Mohanty%2C+Saraju+P%2E%22">Mohanty, Saraju P.</searchLink><relatesTo>2</relatesTo><i> saraju.mohanty@unt.edu</i><br /><searchLink fieldCode="AR" term="%22Banerjee%2C+Shibaji%22">Banerjee, Shibaji</searchLink><relatesTo>1</relatesTo><i> shibaji100@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Pradhan%2C+Dhiraj+K%2E%22">Pradhan, Dhiraj K.</searchLink><relatesTo>1</relatesTo><i> pradhan@compsci.bristol.ac.uk</i><br /><searchLink fieldCode="AR" term="%22Jabir%2C+A%2EM%2E%22">Jabir, A.M.</searchLink><relatesTo>3</relatesTo><i> ajabir@brookes.ac.uk</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Computers+%26+Electrical+Engineering%22">Computers & Electrical Engineering</searchLink>. May2013, Vol. 39 Issue 4, p1077-1087. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Cryptography%22">Cryptography</searchLink><br /><searchLink fieldCode="DE" term="%22Cyberterrorism%22">Cyberterrorism</searchLink><br /><searchLink fieldCode="DE" term="%22Switching+circuits%22">Switching circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract: Thwarting severe cryptographic hardware attacks requires new approaches to logic and physical designs. This paper presents a systematic design approach to fault tolerant cryptographic hardware designs by combining the concurrent error detection and correction, and uniform switching activity cells. The effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance of stream cipher algorithms with error detection and correction was studied by synthesising the designs on FPGA and custom Integrated Circuits. The hardware building blocks are investigated to minimise switching activity of a circuit for all possible inputs and their transitions by adding redundant gates and increasing the overall number of signal transitions. The overheads of the proposed approach are also discussed. [Copyright &y& Elsevier] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Computers & Electrical Engineering is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.compeleceng.2013.01.001 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 1077 Subjects: – SubjectFull: Concurrent error detection Type: general – SubjectFull: Cryptography Type: general – SubjectFull: Cyberterrorism Type: general – SubjectFull: Switching circuits Type: general – SubjectFull: Fault tolerance (Engineering) Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Signal processing Type: general Titles: – TitleFull: Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Mathew, Jimson – PersonEntity: Name: NameFull: Mohanty, Saraju P. – PersonEntity: Name: NameFull: Banerjee, Shibaji – PersonEntity: Name: NameFull: Pradhan, Dhiraj K. – PersonEntity: Name: NameFull: Jabir, A.M. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 00457906 Numbering: – Type: volume Value: 39 – Type: issue Value: 4 Titles: – TitleFull: Computers & Electrical Engineering Type: main |
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