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Automating Stressmark Generation for Testing Processor Voltage Fluctuations.

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Title: Automating Stressmark Generation for Testing Processor Voltage Fluctuations.
Authors: Kim, Youngtaek1, John, Lizy Kurian1, Pant, Sanjay2, Manne, Srilatha2, Schulte, Michael2, Bircher, W. Lloyd2, Govindan, Madhu Saravana Sibi2
Source: IEEE Micro. Jul2013, Vol. 33 Issue 4, p66-75. 10p.
Subjects: Microprocessors, Microprocessor energy consumption, Electric potential, Electric power, Power distribution networks, Multicore processors, Central processing units, Power resources
Abstract: Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems. [ABSTRACT FROM PUBLISHER]
ISSN:02721732
DOI:10.1109/MM.2013.70