Automating Stressmark Generation for Testing Processor Voltage Fluctuations.
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| Title: | Automating Stressmark Generation for Testing Processor Voltage Fluctuations. |
|---|---|
| Authors: | Kim, Youngtaek1, John, Lizy Kurian1, Pant, Sanjay2, Manne, Srilatha2, Schulte, Michael2, Bircher, W. Lloyd2, Govindan, Madhu Saravana Sibi2 |
| Source: | IEEE Micro. Jul2013, Vol. 33 Issue 4, p66-75. 10p. |
| Subjects: | Microprocessors, Microprocessor energy consumption, Electric potential, Electric power, Power distribution networks, Multicore processors, Central processing units, Power resources |
| Abstract: | Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 89975686 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Automating Stressmark Generation for Testing Processor Voltage Fluctuations. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kim%2C+Youngtaek%22">Kim, Youngtaek</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22John%2C+Lizy+Kurian%22">John, Lizy Kurian</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Pant%2C+Sanjay%22">Pant, Sanjay</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Manne%2C+Srilatha%22">Manne, Srilatha</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Schulte%2C+Michael%22">Schulte, Michael</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Bircher%2C+W%2E+Lloyd%22">Bircher, W. Lloyd</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Govindan%2C+Madhu+Saravana+Sibi%22">Govindan, Madhu Saravana Sibi</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Micro%22">IEEE Micro</searchLink>. Jul2013, Vol. 33 Issue 4, p66-75. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+energy+consumption%22">Microprocessor energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+potential%22">Electric potential</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+power%22">Electric power</searchLink><br /><searchLink fieldCode="DE" term="%22Power+distribution+networks%22">Power distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Multicore+processors%22">Multicore processors</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Power+resources%22">Power resources</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/MM.2013.70 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 66 Subjects: – SubjectFull: Microprocessors Type: general – SubjectFull: Microprocessor energy consumption Type: general – SubjectFull: Electric potential Type: general – SubjectFull: Electric power Type: general – SubjectFull: Power distribution networks Type: general – SubjectFull: Multicore processors Type: general – SubjectFull: Central processing units Type: general – SubjectFull: Power resources Type: general Titles: – TitleFull: Automating Stressmark Generation for Testing Processor Voltage Fluctuations. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kim, Youngtaek – PersonEntity: Name: NameFull: John, Lizy Kurian – PersonEntity: Name: NameFull: Pant, Sanjay – PersonEntity: Name: NameFull: Manne, Srilatha – PersonEntity: Name: NameFull: Schulte, Michael – PersonEntity: Name: NameFull: Bircher, W. Lloyd – PersonEntity: Name: NameFull: Govindan, Madhu Saravana Sibi IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 02721732 Numbering: – Type: volume Value: 33 – Type: issue Value: 4 Titles: – TitleFull: IEEE Micro Type: main |
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