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Resilient High-Performance Processors with Spare RIBs.

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Title: Resilient High-Performance Processors with Spare RIBs.
Authors: Palframan, David J.1, Kim, Nam Sung1, Lipasti, Mikko H.1
Source: IEEE Micro. Jul2013, Vol. 33 Issue 4, p26-34. 9p.
Subjects: Microprocessor energy consumption, Multiplexing, Data transmission systems, Stochastic processes, Fault tolerance (Engineering), Reliability in engineering
Abstract: Resilience to defects and parametric variations is of the utmost concern for future technology generations. Traditional redundancy to repair defects, however, can incur performance penalties owing to multiplexing. This article presents a processor design that incorporates bit-sliced redundancy along the data path. This approach makes it possible to tolerate defects without hurting performance, because the same bit offset is left unused throughout the execution core. In addition, the authors use this approach to enhance performance by avoiding excessively slow critical paths created by random delay variations. Adding a single bit slice, for instance, can reduce the delay overhead of random process variations by 10 percent while providing fault tolerance for 15 percent of the execution core. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Resilience to defects and parametric variations is of the utmost concern for future technology generations. Traditional redundancy to repair defects, however, can incur performance penalties owing to multiplexing. This article presents a processor design that incorporates bit-sliced redundancy along the data path. This approach makes it possible to tolerate defects without hurting performance, because the same bit offset is left unused throughout the execution core. In addition, the authors use this approach to enhance performance by avoiding excessively slow critical paths created by random delay variations. Adding a single bit slice, for instance, can reduce the delay overhead of random process variations by 10 percent while providing fault tolerance for 15 percent of the execution core. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/MM.2013.72
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      – SubjectFull: Microprocessor energy consumption
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      – SubjectFull: Multiplexing
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      – SubjectFull: Data transmission systems
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      – SubjectFull: Stochastic processes
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      – SubjectFull: Fault tolerance (Engineering)
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      – SubjectFull: Reliability in engineering
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              Text: Jul2013
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