A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.
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| Title: | A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. |
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| Authors: | Chang, Meng-Fan1, Chen, Ming-Pin2, Chen, Lai-Fu2, Yang, Shu-Meng2, Kuo, Yao-Jen2, Wu, Jui-Jen2, Su, Hsiu-Yun3, Chu, Yuan-Hua3, Wu, Wen-Ching3, Yang, Tzu-Yi3, Yamauchi, Hiroyuki4 |
| Source: | IEEE Journal of Solid-State Circuits. Oct2013, Vol. 48 Issue 10, p2558-2569. 12p. |
| Subjects: | Static random access memory chips, Integrated memory circuits, Low voltage integrated circuits, Transistors, Offset reflector antennas, Amplitude variation with offset analysis |
| Abstract: | In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A\astVDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-VTH, (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both ‘High’ and ‘Low’ sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A\astVDDmin is ~50% lower than that of conventional 8T SRAM devices. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
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| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 90676471 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Chang%2C+Meng-Fan%22">Chang, Meng-Fan</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Ming-Pin%22">Chen, Ming-Pin</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Lai-Fu%22">Chen, Lai-Fu</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Yang%2C+Shu-Meng%22">Yang, Shu-Meng</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Kuo%2C+Yao-Jen%22">Kuo, Yao-Jen</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Wu%2C+Jui-Jen%22">Wu, Jui-Jen</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Su%2C+Hsiu-Yun%22">Su, Hsiu-Yun</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Chu%2C+Yuan-Hua%22">Chu, Yuan-Hua</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Wu%2C+Wen-Ching%22">Wu, Wen-Ching</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Yang%2C+Tzu-Yi%22">Yang, Tzu-Yi</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Yamauchi%2C+Hiroyuki%22">Yamauchi, Hiroyuki</searchLink><relatesTo>4</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Oct2013, Vol. 48 Issue 10, p2558-2569. 12p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Low+voltage+integrated+circuits%22">Low voltage integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Offset+reflector+antennas%22">Offset reflector antennas</searchLink><br /><searchLink fieldCode="DE" term="%22Amplitude+variation+with+offset+analysis%22">Amplitude variation with offset analysis</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A\astVDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-VTH, (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both ‘High’ and ‘Low’ sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A\astVDDmin is ~50% lower than that of conventional 8T SRAM devices. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/JSSC.2013.2273835 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 12 StartPage: 2558 Subjects: – SubjectFull: Static random access memory chips Type: general – SubjectFull: Integrated memory circuits Type: general – SubjectFull: Low voltage integrated circuits Type: general – SubjectFull: Transistors Type: general – SubjectFull: Offset reflector antennas Type: general – SubjectFull: Amplitude variation with offset analysis Type: general Titles: – TitleFull: A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Chang, Meng-Fan – PersonEntity: Name: NameFull: Chen, Ming-Pin – PersonEntity: Name: NameFull: Chen, Lai-Fu – PersonEntity: Name: NameFull: Yang, Shu-Meng – PersonEntity: Name: NameFull: Kuo, Yao-Jen – PersonEntity: Name: NameFull: Wu, Jui-Jen – PersonEntity: Name: NameFull: Su, Hsiu-Yun – PersonEntity: Name: NameFull: Chu, Yuan-Hua – PersonEntity: Name: NameFull: Wu, Wen-Ching – PersonEntity: Name: NameFull: Yang, Tzu-Yi – PersonEntity: Name: NameFull: Yamauchi, Hiroyuki IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 00189200 Numbering: – Type: volume Value: 48 – Type: issue Value: 10 Titles: – TitleFull: IEEE Journal of Solid-State Circuits Type: main |
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