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Limits of Parallelism and Boosting in Dim Silicon.

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Title: Limits of Parallelism and Boosting in Dim Silicon.
Authors: Pinckney, Nathaniel1, Dreslinski, Ronald G.1, Sewell, Korey1, Fick, David1, Mudge, Trevor1, Sylvester, Dennis1, Blaauw, David1
Source: IEEE Micro. Sep2013, Vol. 33 Issue 5, p30-37. 8p.
Subjects: Silicon research, Nonmetals, Electric potential, Electrostatics, Technology
Abstract: Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be executed simultaneously within thermal limits. In this article, the authors investigate the limit of voltage scaling together with task parallelization to maintain task completion latency while reducing energy consumption. Additionally, they examine improvements in energy efficiency and parallelism when serial portions of code can be overcome through quickly boosting a core's operating voltage. When accounting for parallelization overheads, minimum task energy is obtained at near-threshold supply voltages across six commercial technology nodes and provides 4× improvement in overall CMP performance. Boosting is most effective when the task is modestly parallelizable but not highly parallelizable. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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PubType: Academic Journal
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  Data: Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be executed simultaneously within thermal limits. In this article, the authors investigate the limit of voltage scaling together with task parallelization to maintain task completion latency while reducing energy consumption. Additionally, they examine improvements in energy efficiency and parallelism when serial portions of code can be overcome through quickly boosting a core's operating voltage. When accounting for parallelization overheads, minimum task energy is obtained at near-threshold supply voltages across six commercial technology nodes and provides 4× improvement in overall CMP performance. Boosting is most effective when the task is modestly parallelizable but not highly parallelizable. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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