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Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers.

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Title: Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers.
Authors: Yoshida, Toshio1, Maruyama, Takumi1, Akizuki, Yasunobu1, Kan, Ryuji1, Kiyota, Naohiro1, Ikenishi, Kiyoshi1, Itou, Shigeki1, Watahiki, Tomoyuki1, Okano, Hiroshi2
Source: IEEE Micro. Nov2013, Vol. 33 Issue 6, p16-24. 9p.
Subjects: Computer architecture, Unix operating systems, Computer operating systems, Computer engineering, Cryptography research
Abstract: Fujitsu's Sparc64 X is a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, I/O controllers, and system controllers for connecting multiple chips. The authors of this article enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer. The peak memory bandwidth is 102 Gbytes per second. These features realize extremely high-throughput performance. In addition, the authors added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. They call these functions "software on chip" (SWoC). Furthermore, they employ high-reliability technology used in mainframes to ensure stable operation of mission-critical systems. This article describes the past and current direction of the microarchitecture of the Sparc64 processor series, gives an overview of Sparc64 X, and presents results of testing the performance and power efficiency of SWoC. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Micro%22">IEEE Micro</searchLink>. Nov2013, Vol. 33 Issue 6, p16-24. 9p.
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  Data: <searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Unix+operating+systems%22">Unix operating systems</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+operating+systems%22">Computer operating systems</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Cryptography+research%22">Cryptography research</searchLink>
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  Data: Fujitsu's Sparc64 X is a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, I/O controllers, and system controllers for connecting multiple chips. The authors of this article enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer. The peak memory bandwidth is 102 Gbytes per second. These features realize extremely high-throughput performance. In addition, the authors added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. They call these functions "software on chip" (SWoC). Furthermore, they employ high-reliability technology used in mainframes to ensure stable operation of mission-critical systems. This article describes the past and current direction of the microarchitecture of the Sparc64 processor series, gives an overview of Sparc64 X, and presents results of testing the performance and power efficiency of SWoC. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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