WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.
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| Title: | WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. |
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| Authors: | Huang, Yazhi1, Shi, Liang1, Li, Jianhua1, Li, Qingan1, Xue, Chun Jason1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2014, Vol. 22 Issue 1, p168-180. 13p. |
| Subjects: | Embedded computer system design & construction, Computer software execution, Architecture Analysis & Design Language, Microprocessor programming, Computer scheduling, Optimizing compilers |
| Abstract: | Worst-case execution time (WCET) is one of the most important metric in real-time embedded system design. For embedded systems with clustered very long instruction word (VLIW) architecture, register allocation, instruction scheduling, and cluster assignment are three key activities for code optimization, which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem, i.e., independently performing register allocation, scheduling, and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled code. In this paper, a compiler level optimization, namely WCET-aware re-scheduling register allocation, is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling, and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 34% on average. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 93317416 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Huang%2C+Yazhi%22">Huang, Yazhi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Shi%2C+Liang%22">Shi, Liang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Li%2C+Jianhua%22">Li, Jianhua</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Li%2C+Qingan%22">Li, Qingan</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Xue%2C+Chun+Jason%22">Xue, Chun Jason</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Jan2014, Vol. 22 Issue 1, p168-180. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Embedded+computer+system+design+%26+construction%22">Embedded computer system design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software+execution%22">Computer software execution</searchLink><br /><searchLink fieldCode="DE" term="%22Architecture+Analysis+%26+Design+Language%22">Architecture Analysis & Design Language</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+programming%22">Microprocessor programming</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+scheduling%22">Computer scheduling</searchLink><br /><searchLink fieldCode="DE" term="%22Optimizing+compilers%22">Optimizing compilers</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Worst-case execution time (WCET) is one of the most important metric in real-time embedded system design. For embedded systems with clustered very long instruction word (VLIW) architecture, register allocation, instruction scheduling, and cluster assignment are three key activities for code optimization, which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem, i.e., independently performing register allocation, scheduling, and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled code. In this paper, a compiler level optimization, namely WCET-aware re-scheduling register allocation, is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling, and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 34% on average. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2012.2236114 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 168 Subjects: – SubjectFull: Embedded computer system design & construction Type: general – SubjectFull: Computer software execution Type: general – SubjectFull: Architecture Analysis & Design Language Type: general – SubjectFull: Microprocessor programming Type: general – SubjectFull: Computer scheduling Type: general – SubjectFull: Optimizing compilers Type: general Titles: – TitleFull: WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Huang, Yazhi – PersonEntity: Name: NameFull: Shi, Liang – PersonEntity: Name: NameFull: Li, Jianhua – PersonEntity: Name: NameFull: Li, Qingan – PersonEntity: Name: NameFull: Xue, Chun Jason IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2014 Type: published Y: 2014 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 22 – Type: issue Value: 1 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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