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Hardware support for memory protection in sensor nodes.

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Title: Hardware support for memory protection in sensor nodes.
Authors: Lopriore, Lanfranco1 l.lopriore@iet.unipi.it
Source: Microprocessors & Microsystems. May2014, Vol. 38 Issue 3, p226-232. 7p.
Subjects: Computer input-output equipment, Memory maps (Computer science), Wireless sensor nodes, Microcontrollers, Computer software execution, Microprocessors
Abstract: Abstract: With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings. [Copyright &y& Elsevier]
Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 95383425
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: Hardware support for memory protection in sensor nodes.
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  Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. May2014, Vol. 38 Issue 3, p226-232. 7p.
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  Data: <searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Memory+maps+%28Computer+science%29%22">Memory maps (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Wireless+sensor+nodes%22">Wireless sensor nodes</searchLink><br /><searchLink fieldCode="DE" term="%22Microcontrollers%22">Microcontrollers</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software+execution%22">Computer software execution</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink>
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  Data: Abstract: With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings. [Copyright &y& Elsevier]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.micpro.2014.01.004
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      – Code: eng
        Text: English
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        PageCount: 7
        StartPage: 226
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      – SubjectFull: Computer input-output equipment
        Type: general
      – SubjectFull: Memory maps (Computer science)
        Type: general
      – SubjectFull: Wireless sensor nodes
        Type: general
      – SubjectFull: Microcontrollers
        Type: general
      – SubjectFull: Computer software execution
        Type: general
      – SubjectFull: Microprocessors
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      – TitleFull: Hardware support for memory protection in sensor nodes.
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              Text: May2014
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            – TitleFull: Microprocessors & Microsystems
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