A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization.
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| Title: | A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization. |
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| Authors: | Kelefouras, Vasilios1 kelefouras@ece.upatras.gr, Kritikakou, Angeliki1, Goutis, Costas1 |
| Source: | Journal of Supercomputing. Apr2014, Vol. 68 Issue 1, p459-487. 29p. |
| Subjects: | Library software, Memory hierarchy (Computer science), Field programmable gate arrays, Computer vision, Computer storage devices |
| Abstract: | In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 95573152 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kelefouras%2C+Vasilios%22">Kelefouras, Vasilios</searchLink><relatesTo>1</relatesTo><i> kelefouras@ece.upatras.gr</i><br /><searchLink fieldCode="AR" term="%22Kritikakou%2C+Angeliki%22">Kritikakou, Angeliki</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Goutis%2C+Costas%22">Goutis, Costas</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Apr2014, Vol. 68 Issue 1, p459-487. 29p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Library+software%22">Library software</searchLink><br /><searchLink fieldCode="DE" term="%22Memory+hierarchy+%28Computer+science%29%22">Memory hierarchy (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+vision%22">Computer vision</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-013-1049-x Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 29 StartPage: 459 Subjects: – SubjectFull: Library software Type: general – SubjectFull: Memory hierarchy (Computer science) Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Computer vision Type: general – SubjectFull: Computer storage devices Type: general Titles: – TitleFull: A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kelefouras, Vasilios – PersonEntity: Name: NameFull: Kritikakou, Angeliki – PersonEntity: Name: NameFull: Goutis, Costas IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2014 Type: published Y: 2014 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 68 – Type: issue Value: 1 Titles: – TitleFull: Journal of Supercomputing Type: main |
| ResultId | 1 |
