APA (7th ed.) Citation

Ramprasath, S., & Vasudevan, V. (2014). Statistical Criticality Computation Using the Circuit Delay. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 33(5), 717. https://doi.org/10.1109/TCAD.2013.2296436

Chicago Style (17th ed.) Citation

Ramprasath, S., and V. Vasudevan. "Statistical Criticality Computation Using the Circuit Delay." IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 33, no. 5 (2014): 717. https://doi.org/10.1109/TCAD.2013.2296436.

MLA (9th ed.) Citation

Ramprasath, S., and V. Vasudevan. "Statistical Criticality Computation Using the Circuit Delay." IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 33, no. 5, 2014, p. 717, https://doi.org/10.1109/TCAD.2013.2296436.