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Statistical Criticality Computation Using the Circuit Delay.

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Title: Statistical Criticality Computation Using the Circuit Delay.
Authors: Ramprasath, S.1, Vasudevan, V.1
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. May2014, Vol. 33 Issue 5, p717-727. 11p.
Subjects: Integrated circuits, Delay lines, Critical path analysis, Algorithms, Mathematical programming
Abstract: The statistical nature of gate delays in current day technologies necessitates the use of measures, such as path criticality and node/edge criticality for timing optimization. Node criticalities are typically computed using the complementary path delay. An alternative approach to compute the criticality using the circuit delay has been recently proposed. In this paper, we discuss in detail, the use of circuit delay to compute node criticalities and show that the criticality thus found is not equal to the conventional measure found using complementary path delay. However, there is a monotonic relationship between them and the two measures can be used interchangeably. We derive new bounds for the global criticality and propose a pruning algorithm based on these bounds to improve the accuracy and speed of computation. The use of this pruning technique results in a significant speedup in criticality computations. We obtain an order of magnitude average speedup for ISCAS benchmarks. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
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  Data: Statistical Criticality Computation Using the Circuit Delay.
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  Data: The statistical nature of gate delays in current day technologies necessitates the use of measures, such as path criticality and node/edge criticality for timing optimization. Node criticalities are typically computed using the complementary path delay. An alternative approach to compute the criticality using the circuit delay has been recently proposed. In this paper, we discuss in detail, the use of circuit delay to compute node criticalities and show that the criticality thus found is not equal to the conventional measure found using complementary path delay. However, there is a monotonic relationship between them and the two measures can be used interchangeably. We derive new bounds for the global criticality and propose a pruning algorithm based on these bounds to improve the accuracy and speed of computation. The use of this pruning technique results in a significant speedup in criticality computations. We obtain an order of magnitude average speedup for ISCAS benchmarks. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TCAD.2013.2296436
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        Text: English
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        PageCount: 11
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      – SubjectFull: Integrated circuits
        Type: general
      – SubjectFull: Delay lines
        Type: general
      – SubjectFull: Critical path analysis
        Type: general
      – SubjectFull: Algorithms
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      – SubjectFull: Mathematical programming
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      – TitleFull: Statistical Criticality Computation Using the Circuit Delay.
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