APA (7th ed.) Citation

Verries, J., & Sahraoui, A. (2013). Case Study On SYSML and VHDL-AMS for Designing and Validating Systems. Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I, 1.

Chicago Style (17th ed.) Citation

Verries, J., and A. Sahraoui. "Case Study On SYSML and VHDL-AMS for Designing and Validating Systems." Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I 2013: 1.

MLA (9th ed.) Citation

Verries, J., and A. Sahraoui. "Case Study On SYSML and VHDL-AMS for Designing and Validating Systems." Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I, 2013, p. 1.