Bibliographic Details
| Title: |
Case Study On SYSML and VHDL-AMS for Designing and Validating Systems. |
| Authors: |
Verries, J.1, Sahraoui, A.1 ahraoui@mail.fr |
| Source: |
Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I. 2013, p1-6. 6p. |
| Subjects: |
SysML (Computer science), VHDL (Computer hardware description language), Computer science, Computer software development, Systems engineering |
| Abstract: |
An approach combining SysML and VHDL-AMS is proposed in this paper. The design is modeled with SysML and then we derive some intuitive rules to obtain the VHDLAMS model of the lower level blocks built in SysML. The work is at the level of the tentative approach that is being carried out on real industrial application for onboard systems. The paper goes beyond the models issues and carries out the simulation procedure that are available on tools to validate the design for the intended blocks. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
