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Case Study On SYSML and VHDL-AMS for Designing and Validating Systems.

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Title: Case Study On SYSML and VHDL-AMS for Designing and Validating Systems.
Authors: Verries, J.1, Sahraoui, A.1 ahraoui@mail.fr
Source: Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I. 2013, p1-6. 6p.
Subjects: SysML (Computer science), VHDL (Computer hardware description language), Computer science, Computer software development, Systems engineering
Abstract: An approach combining SysML and VHDL-AMS is proposed in this paper. The design is modeled with SysML and then we derive some intuitive rules to obtain the VHDLAMS model of the lower level blocks built in SysML. The work is at the level of the tentative approach that is being carried out on real industrial application for onboard systems. The paper goes beyond the models issues and carries out the simulation procedure that are available on tools to validate the design for the intended blocks. [ABSTRACT FROM AUTHOR]
Copyright of Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 96451368
AccessLevel: 6
PubType: Conference
PubTypeId: conference
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  Data: Case Study On SYSML and VHDL-AMS for Designing and Validating Systems.
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  Data: <searchLink fieldCode="AR" term="%22Verries%2C+J%2E%22">Verries, J.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Sahraoui%2C+A%2E%22">Sahraoui, A.</searchLink><relatesTo>1</relatesTo><i> ahraoui@mail.fr</i>
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  Data: <searchLink fieldCode="JN" term="%22Proceedings+of+the+World+Congress+on+Engineering+%26+Computer+Science+2013+Volume+I%22">Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I</searchLink>. 2013, p1-6. 6p.
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  Data: <searchLink fieldCode="DE" term="%22SysML+%28Computer+science%29%22">SysML (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22VHDL+%28Computer+hardware+description+language%29%22">VHDL (Computer hardware description language)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+science%22">Computer science</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software+development%22">Computer software development</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+engineering%22">Systems engineering</searchLink>
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  Label: Abstract
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  Data: An approach combining SysML and VHDL-AMS is proposed in this paper. The design is modeled with SysML and then we derive some intuitive rules to obtain the VHDLAMS model of the lower level blocks built in SysML. The work is at the level of the tentative approach that is being carried out on real industrial application for onboard systems. The paper goes beyond the models issues and carries out the simulation procedure that are available on tools to validate the design for the intended blocks. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Code: eng
        Text: English
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        PageCount: 6
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      – SubjectFull: SysML (Computer science)
        Type: general
      – SubjectFull: VHDL (Computer hardware description language)
        Type: general
      – SubjectFull: Computer science
        Type: general
      – SubjectFull: Computer software development
        Type: general
      – SubjectFull: Systems engineering
        Type: general
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      – TitleFull: Case Study On SYSML and VHDL-AMS for Designing and Validating Systems.
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            NameFull: Verries, J.
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            NameFull: Sahraoui, A.
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            – D: 01
              M: 07
              Text: 2013
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              Y: 2013
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            – TitleFull: Proceedings of the World Congress on Engineering & Computer Science 2013 Volume I
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