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Efficient Register Renaming and Recovery for High-Performance Processors.

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Title: Efficient Register Renaming and Recovery for High-Performance Processors.
Authors: Petit, Salvador1, Ubal, Rafael2, Sahuquillo, Julio1, Lopez, Pedro1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jul2014, Vol. 22 Issue 7, p1506-1514. 9p.
Subjects: Microprocessor performance, Random access memory, Associative storage, Registers (Computers), Energy consumption of computers
Abstract: Modern superscalar processors implement register renaming using either random access memory (RAM) or content-addressable memories (CAM) tables. The design of these structures should address both access time and misprediction recovery penalty. Although direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. The presence of associative ports in CAMs, however, prevents them from scaling with the number of physical registers and pipeline width, negatively impacting performance, area, and energy consumption at the rename stage. In this paper, we present a new hybrid RAM–CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides fast and energy-efficient access to register mappings. On misspeculation, a low-complexity CAM enables immediate recovery. Experimental results show that in a four-way state-of-the-art superscalar processor, the new approach provides almost the same performance as an ideal CAM-based renaming scheme, while dissipating only between 17% and 26% of the original energy and, in some cases, consuming less energy than purely RAM-based renaming schemes. Overall, the silicon area required to implement the hybrid RAM–CAM scheme does not exceed the area required by conventional renaming mechanisms. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Efficient Register Renaming and Recovery for High-Performance Processors.
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  Data: <searchLink fieldCode="DE" term="%22Microprocessor+performance%22">Microprocessor performance</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Associative+storage%22">Associative storage</searchLink><br /><searchLink fieldCode="DE" term="%22Registers+%28Computers%29%22">Registers (Computers)</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption+of+computers%22">Energy consumption of computers</searchLink>
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  Data: Modern superscalar processors implement register renaming using either random access memory (RAM) or content-addressable memories (CAM) tables. The design of these structures should address both access time and misprediction recovery penalty. Although direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. The presence of associative ports in CAMs, however, prevents them from scaling with the number of physical registers and pipeline width, negatively impacting performance, area, and energy consumption at the rename stage. In this paper, we present a new hybrid RAM–CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides fast and energy-efficient access to register mappings. On misspeculation, a low-complexity CAM enables immediate recovery. Experimental results show that in a four-way state-of-the-art superscalar processor, the new approach provides almost the same performance as an ideal CAM-based renaming scheme, while dissipating only between 17% and 26% of the original energy and, in some cases, consuming less energy than purely RAM-based renaming schemes. Overall, the silicon area required to implement the hybrid RAM–CAM scheme does not exceed the area required by conventional renaming mechanisms. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2013.2270001
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        Text: English
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        Type: general
      – SubjectFull: Random access memory
        Type: general
      – SubjectFull: Associative storage
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      – SubjectFull: Registers (Computers)
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      – SubjectFull: Energy consumption of computers
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      – TitleFull: Efficient Register Renaming and Recovery for High-Performance Processors.
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              Text: Jul2014
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