A star network approach in heterogeneous multiprocessors system on chip.

Saved in:

Bibliographic Details
Title:	A star network approach in heterogeneous multiprocessors system on chip.
Authors:	Wang, Chao¹ saintwc@mail.ustc.edu.cn, Li, Xi² llxx@ustc.edu.cn, Zhang, Junneng¹ zjneng@mail.ustc.edu.cn, Zhou, Xuehai² xhzhou@ustc.edu.cn, Wang, Aili² wangal@ustc.edu.cn
Source:	Journal of Supercomputing. Dec2012, Vol. 62 Issue 3, p1404-1424. 21p.
Subjects:	Multiprocessors, Multiprogramming (Electronic computers), Central processing units, Electronic data processing, Systems on a chip
Abstract:	Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA. [ABSTRACT FROM AUTHOR]
	Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database:	Engineering Source

Description
Abstract:	Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA. [ABSTRACT FROM AUTHOR]
ISSN:	09208542
DOI:	10.1007/s11227-012-0810-x