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A star network approach in heterogeneous multiprocessors system on chip.

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Title: A star network approach in heterogeneous multiprocessors system on chip.
Authors: Wang, Chao1 saintwc@mail.ustc.edu.cn, Li, Xi2 llxx@ustc.edu.cn, Zhang, Junneng1 zjneng@mail.ustc.edu.cn, Zhou, Xuehai2 xhzhou@ustc.edu.cn, Wang, Aili2 wangal@ustc.edu.cn
Source: Journal of Supercomputing. Dec2012, Vol. 62 Issue 3, p1404-1424. 21p.
Subjects: Multiprocessors, Multiprogramming (Electronic computers), Central processing units, Electronic data processing, Systems on a chip
Abstract: Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  – Type: pdflink
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  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 99372453
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: A star network approach in heterogeneous multiprocessors system on chip.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Wang%2C+Chao%22">Wang, Chao</searchLink><relatesTo>1</relatesTo><i> saintwc@mail.ustc.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Li%2C+Xi%22">Li, Xi</searchLink><relatesTo>2</relatesTo><i> llxx@ustc.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Junneng%22">Zhang, Junneng</searchLink><relatesTo>1</relatesTo><i> zjneng@mail.ustc.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Xuehai%22">Zhou, Xuehai</searchLink><relatesTo>2</relatesTo><i> xhzhou@ustc.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Wang%2C+Aili%22">Wang, Aili</searchLink><relatesTo>2</relatesTo><i> wangal@ustc.edu.cn</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Dec2012, Vol. 62 Issue 3, p1404-1424. 21p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Multiprocessors%22">Multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprogramming+%28Electronic+computers%29%22">Multiprogramming (Electronic computers)</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+data+processing%22">Electronic data processing</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2 % Flip Flops and 2.45 % LUTs of a single FPGA. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s11227-012-0810-x
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 21
        StartPage: 1404
    Subjects:
      – SubjectFull: Multiprocessors
        Type: general
      – SubjectFull: Multiprogramming (Electronic computers)
        Type: general
      – SubjectFull: Central processing units
        Type: general
      – SubjectFull: Electronic data processing
        Type: general
      – SubjectFull: Systems on a chip
        Type: general
    Titles:
      – TitleFull: A star network approach in heterogeneous multiprocessors system on chip.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Wang, Chao
      – PersonEntity:
          Name:
            NameFull: Li, Xi
      – PersonEntity:
          Name:
            NameFull: Zhang, Junneng
      – PersonEntity:
          Name:
            NameFull: Zhou, Xuehai
      – PersonEntity:
          Name:
            NameFull: Wang, Aili
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 12
              Text: Dec2012
              Type: published
              Y: 2012
          Identifiers:
            – Type: issn-print
              Value: 09208542
          Numbering:
            – Type: volume
              Value: 62
            – Type: issue
              Value: 3
          Titles:
            – TitleFull: Journal of Supercomputing
              Type: main
ResultId 1